数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CS4360 数据表(PDF) 10 Page - Cirrus Logic

部件名 CS4360
功能描述  24-Bit, 192 kHz 6 Channel D/A Converter?
PDF  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS4360 数据表(HTML) 10 Page - Cirrus Logic

Back Button CS4360 Datasheet HTML 6Page - Cirrus Logic CS4360 Datasheet HTML 7Page - Cirrus Logic CS4360 Datasheet HTML 8Page - Cirrus Logic CS4360 Datasheet HTML 9Page - Cirrus Logic CS4360 Datasheet HTML 10Page - Cirrus Logic CS4360 Datasheet HTML 11Page - Cirrus Logic CS4360 Datasheet HTML 12Page - Cirrus Logic CS4360 Datasheet HTML 13Page - Cirrus Logic CS4360 Datasheet HTML 14Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 36 page
background image
CS4360
10
DS517PP1
SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT
(Note 16) (For -KS & -KZ parts TA = -10 to +70°C; for -BS & -BZ parts TA = -40 to +85°C; VLC = 1.7 V - 5.5 V;
Inputs: Logic 0 = GND, Logic 1 = VLC, CL =30pF)
Notes: 16. The Two-Wire Format is compatible with the I2C protocol.
17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
19.
for Single-Speed Mode,
for Double-Speed Mode,
for Quad-Speed Mode.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
SDA Hold Time from SCL Falling
(Note 17)
thdd
0-
µs
SDA Setup time to SCL Rising
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trc
-1
µs
Fall Time SCL and SDA
tfc, tfc
-300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
(Note 18)
tack
-
(Note 19)
ns
5
256
Fs
×
---------------------
5
128
Fs
×
---------------------
5
64
Fs
×
------------------
t
buf
t
hdst
t
lo w
t
hdd
t
high
t
sud
Stop
Sta rt
SD A
SCL
t
irs
RST
t
hdst
t
rc
t
fc
t sust
t susp
Sta rt
Stop
R epe ate d
t
rd
t
fd
t
ack
Figure 2. Control Port Timing - Two-Wire Format



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com