CS4360 datasheet(23/36 Pages) CIRRUS

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CS4360

DS517PP1

6. APPLICATIONS

6.1

Grounding and Power Supply

Decoupling

As with any high resolution converter, the CS4360

requires careful attention to power supply and

grounding arrangements to optimize performance.

Figure 4 shows the recommended power arrange-

ment with VA, VD, VLS and VLC connected to

clean supplies. Decoupling capacitors should be lo-

cated as close to the device package as possible. If

desired, all supply pins may be connected to the

same supply, but a decoupling capacitor should still

be placed on each supply pin.

6.2

Oversampling Modes

The CS4360 operates in one of three oversampling

modes based on the input sample rate. Mode selec-

tion is determined by the FM pins in Stand-Alone

mode or the FM bits in Control Port mode. Single-

Speed mode supports input sample rates up to 50

kHz and uses a 128x oversampling ratio. Double-

Speed mode supports input sample rates up to 100

kHz and uses an oversampling ratio of 64x. Quad-

Speed mode supports input sample rates up to 200

kHz and uses an oversampling ratio of 32x.

6.3

Recommended Power-up Sequence

1. Hold RST low until the power supply, master,

and left/right clocks are stable. In this state, the

control port is reset to its default settings and VQ

will remain low.

2. Bring RST high. The device will remain in a low

power state with VQ low and will initiate the

Stand-Alone power-up sequence. The control port

will be accessible at this time. If Control Port oper-

ation is desired, write the CPEN bit prior to the

completion of the Stand-Alone power-up se-

quence, approximately 512 LRCK cycles in Sin-

gle-Speed Mode (1024 LRCK cycles in Double-

Speed Mode, and 2048 LRCK cycles in Quad-

Speed Mode). Writing this bit will halt the Stand-

Alone power-up sequence and initialize the control

port to its default settings. The desired register set-

tings can be loaded while keeping the PDN bit set

to 1.

3. If Control Port Mode is selected via the CPEN

bit, set the PDN bit to 0 which will initiate the pow-

er-up sequence, which requires approximately

50 µS when the POPG bit is set to 0. If the POPG

bit is set to 1, see Section 6.4 for total power-up

timing.

6.4

Popguard® Transient Control

The CS4360 uses a novel technique to minimize

the effects of output transients during power-up

and power-down. This technique, when used with

external DC-blocking capacitors in series with the

audio outputs, minimizes the audio transients com-

monly produced by single-ended single-supply

converters.

When the device is initially powered-up, the audio

outputs, AOUTAx and AOUTBx, are clamped to

GND. Following a delay of approximately 1000

sample periods, each output begins to ramp toward

the quiescent voltage. Approximately 10,000

left/right clock cycles later, the outputs reach VQ

and audio output begins. This gradual voltage

ramping allows time for the external DC-blocking

capacitor to charge to the quiescent voltage, mini-

mizing the power-up transient.

To prevent transients at power-down, the device

must first enter its power-down state. When this oc-

curs, audio output ceases and the internal output

buffers are disconnected from AOUTAx and

AOUTBx. In their place, a soft-start current sink is

substituted which allows the DC-blocking capaci-

tors to slowly discharge. Once this charge is dissi-

pated, the power to the device may be turned off

and the system is ready for the next power-on.

To prevent an audio transient at the next power-on,

it is necessary to ensure that the DC-blocking ca-

pacitors have fully discharged before turning off

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