AN3308 datasheet(10/52 Pages) STMICROELECTRONICS

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Operating modes

AN3308

10/52

Doc ID 18198 Rev 1

2.1

Power-down mode

When the device is in power-down mode, almost all internal blocks of the device are

switched off to minimize power consumption. Digital interfaces (I2C and SPI) are still active

to allow communication with the device. The configuration registers content is preserved

and output data registers are not updated, therefore keeping the last data sampled in

memory before going into power-down mode.

2.2

Normal mode

In normal mode, data are generated at the data rate (ODR) selected through the DR bits

and for the axis enabled through Zen, Yen, and Xen bits of CTRL_REG1. Data generated for

a disabled axis is 00h.

Data interrupt generation is active and configured through the INT1_CFG register.

2.3

Low power mode

While normal mode guarantees higher resolution, low power mode further reduces the

current consumption.

In low power mode, data are generated at the data rate (ODR) selected through the DR bits

and for the axis enabled through the Zen, Yen, and Xen bits of CTRL_REG1. Data

generated for a disabled axis is 00h.

Data interrupt generation is active and configured through the INT1_CFG register.

100

200

400

1250

185

1600

5000

184

Table 4.

Power consumption (

μA) (continued)

ODR(Hz)

Normal mode (

μA)

Low power mode (

μA)

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