AN3308 datasheet(47/52 Pages) STMICROELECTRONICS

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AN3308

First in first out (FIFO) buffer

Doc ID 18198 Rev 1

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condition disappears, the FIFO buffer returns to stream mode because the IA bit becomes

zero. It is suggested to latch the interrupt signal used as the FIFO trigger in order to avoid

losing interrupt events. If the selected interrupt is latched, it is needed to read the register

INT1_SRC to clear the IA bit; after reading, the IA bit takes 2*ODR to go low.

In stream mode the FIFO buffer continues filling, when the buffer is full, the OVRN bit is set

high and the next samples overwrite the oldest. When trigger occurs, two different cases

can be observed:

If the FIFO buffer is already full (OVRN = “1”), it stops collecting data at the first sample

after trigger. FIFO content is composed of #30 samples collected before the trigger

event, the sample that has generated the interrupt event and one sample after trigger.

If FIFO isn’t yet full (initial transient), it continues filling until it is full (OVRN = “1”) and

then, if trigger is still present, it stops collecting data.

Figure 28.

Stream-to-FIFO mode: interrupt not latched

Figure 29.

Stream-to-FIFO mode: interrupt latched

Stream-to-FIFO can be used in order to analyze the samples history that generate an

interrupt; the standard operation is to read FIFO content when FIFO mode is triggered and

FIFO buffer is full and stopped.

AN3308 数据表(PDF) 47 Page - STMicroelectronics