AN3308 datasheet(41/52 Pages) STMICROELECTRONICS

部件名	AN3308

功能描述	This document describes the low-voltage 3-axis digital output linear MEMS accelerometer provided in an LGA package

PDF	52 Pages

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制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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41 / 52 page

AN3308

First in first out (FIFO) buffer

Doc ID 18198 Rev 1

41/52

Figure 23.

FIFO_EN connection block diagram

9.2.2

FIFO control register (0x2E)

This register is dedicated to FIFO mode selection and watermark configuration.

FM[1:0] bits are dedicated to define the FIFO buffer behavior selection:

FM[1:0] = (0,0): Bypass mode

FM[1:0] = (0,1): FIFO mode

FM[1:0] = (1,0): Stream mode

FM[1:0] = (1,1): Stream-to-FIFO mode

The trigger used to activate stream-to-FIFO mode is related to the IA bit value of the

selected INT1_SRC register and does not depend on the interrupt pin value and polarity.

The trigger is generated also if the selected interrupt is not driven to an interrupt pin.

FTH[4:0] bits are intended to define the watermark level; when FIFO content exceeds this

value the WTM bit is set to “1” in the FIFO source register.

Table 36.

FIFO_CTRL_REG

FM1

FM0

FTH4

FTH3

FTH2

FTH1

FTH0

AN3308 数据表(PDF) 41 Page - STMicroelectronics