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AN3308 数据表(PDF) 21 Page - STMicroelectronics

部件名 AN3308
功能描述  This document describes the low-voltage 3-axis digital output linear MEMS accelerometer provided in an LGA package
PDF  52 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

AN3308 数据表(HTML) 21 Page - STMicroelectronics

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AN3308
Inertial interrupt
Doc ID 18198 Rev 1
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6.2
Threshold
Threshold registers define the reference accelerations used by interrupt generation circuitry.
The value of 1 LSB of these 7-bit registers depends on the selected full scale (Table 16).
6.3
Free-fall and wake-up interrupts
The LIS3DH interrupts signal can behave as free-fall and wake-up. Whenever an interrupt
condition is verified, the interrupt signal is generated and by reading the INT1_SRC register
it is possible to understand which condition happened.
The free-fall signal (FF) and wake-up signal (WU) interrupt generation block is represented
in Figure 7.
The FF or WU interrupt generation is selected through the AOI bit in the INT1_CFG register.
If the AOI bit is ‘0’, signals coming from comparators for the axis enabled through the
INT1_CFG register are put in logical OR. In this case, interrupt is generated when at least
one of the enabled axes exceeds the threshold written in module in INT1_THS registers.
Otherwise, if the AOI bit is ‘1’, signals coming from comparators enter a “NAND” port. In this
case an interrupt signal is generated only if all the enabled axes are passing the threshold
written in the INT1_THS register.
LIR1 bits of CTRL_REG3 allow to decide if the interrupt request must be latched or not. If
LIR1 bit is ‘0’ (default value), the interrupt signal goes high when the interrupt condition is
satisfied and returns to low immediately if the interrupt condition is no longer verified.
Otherwise, if the LIR1 bit is ‘1’, whenever an interrupt condition is applied the interrupt signal
remains high even if the condition returns to a non-interrupt status until a reading to the
INT1_SRC register is performed.
The ZHIE, ZLIE, YHIE, YLIE, XHIE, and HLIE bits of the INT1_CFG register allow to decide
on which axis the interrupt decision must be performed and on which direction the threshold
must be passed to generate the interrupt request.
Table 16.
Threshold LSB value
Full scale
Threshold LSB value (mg)
2~16
4~31
8~63
16
~125



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