Operation modes

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Operation modes

Real-world scenarios may cover a wide variety of configurations, using different baud rates,

ratios of transmit/receive and delays between messages. All these factors influence the

choice of the operation mode.

3.1

Polling mode

Polling mode is the simplest possible operating mode, also known as blocking mode. The

CPU is processing a single task, switching to a low power mode during periods of inactivity.

There is almost no processing overhead, allowing to use very low system clock speed.

This mode can be extremely efficient for very simple scenarios, however blocking mode is

effectively blocking the CPU from processing any other tasks, like data processing or

concurrent communication.

3.2

IT mode

The second option is to rely completely on interrupts, waking the CPU for every transferred

the processing split to atomic operations, never blocking the CPU and achieving real-time

responses.

This mode however strains the CPU a little more, adding processing overhead related to

stack and context resuming.

3.3

DMA mode

In DMA mode the CPU is spared of large portion of processing, setting a DMA channel to

move data between the peripheral and the SRAM. The CPU may spend part of the

processing time in Sleep mode. However the DMA cannot wakeup from Stop mode.

3.4

Combined mode examples

Real-world applications usually are a mix of above mentioned modes, the developers

always try to strike the best bargain between conflicting needs.The following examples are

not covered in bundled source codes, they are mentioned purely as inspiration.

3.4.1

Interrupt with polling

Some embedded systems may not be real-time critical and in this case there is an option to

block the CPU for a limited time to process a message frame. Especially in case of

transmission, energy normally used up to process all TC interrupts is saved, the message is

transmitted in blocking mode, possibly with clock speed lowered and power regulator

switched to low power mode (LPRUN). Only approximately half clock speed is required if

the CPU can treat the message in blocking mode. Normal operation is then restored,

preferably waiting for incoming reply interrupt in Stop mode.