DocID027290 Rev 1

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AN4635

Other considerations

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due to delays in fetching instructions from the program memory and storing the data in the

memory. Usually it is better to slow down the system clock than to set an AHB prescaler

(Section 6.6).

Slowing down the APB limits the bandwidth between the LPUART peripheral and the core.

This is usually not a problem since the amount of data transferred is low. Especially in case

of DMA transfers it is not an issue. In case of CPU driven transfers the core may be stalled

waiting for the bus transfer to complete. This causes the overall energy budget for the

operation to increase in extreme cases. Also, if the bus transfer is not complete, the core is

prevented from going to a low power mode such as Stop or Sleep modes. In case of

LPUART example coming along with this AN it is usually safe to set a APB prescaler value

of 4 but higher values are likely to cause problems and provide no power consumption

advantage (Section 6.7).

4.3

Power configuration

This section deals with practical implications when configuring power modes for LPUART

communication, for complete information please read the dedicated section in RM0376.

4.3.1

Use of Stop and Sleep modes

It is a paradigm in embedded software that during the idle time the CPU should not run and

actively check on flags, but to switch to low power mode, suspend clock, and only resume

operation on external interrupt or event.

This is in case of ARM MCUs achieved by executing WFE or WFI instruction. The L series

of STM32 microcontrollers offer highly configurable selection of idle modes, summarized in

the table 24 of RM0376. The great advantage of LPUART is the ability to take advantage of

Stop mode when waiting for message reception (Section 6.1).

If application doesn’t use VREFINT frequently and spends most of the time in low power

mode, configure ultralow power mode with fast wakeup (ULP and FWU bit in PWR

configuration register). Even in applications that make some use of internal voltage

reference it may be interesting to switch it off and only check the startup time when

measurement is needed. However mind that VREFINT startup requires some additional

energy. For short periods of low power mode (i.e. Sleep mode between bytes typically) there

is no point turning it off and on again, the overall energy budget would grow.

Note:

Ultra-low power mode without fast wakeup is unable to keep the LPUART Tx register fed, or

to keep up with incoming data in blocking and interrupt mode, even with 9600 baud

communication speed.

In most cases it is also desirable to activate the Sleep mode between processing individual

bytes. In case or data reception even Stop mode is available (Section 6.4). This practice

offers great advantage at higher clock speeds, but at core clock speeds near the bare

minimum needed for communication it cannot be recommended. The overhead related to

putting device to Sleep mode and waking it causes a slight increase of power consumption

which is then not balanced by the very short time spent in low power mode (Section 6.2).

4.3.2

Run time configuration

The voltage regulator settings are very important. Use the core voltage scaling as much as

possible (see dedicated figure in RM0376). Switching from range 1 to range 3 is an easy

way to lower typical consumed power by more than 25% (Section 6.11).