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AN4635 数据表(PDF) 10 Page - STMicroelectronics |
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AN4635 数据表(HTML) 10 Page - STMicroelectronics |
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10 / 34 page ![]() Other considerations AN4635 10/34 DocID027290 Rev 1 4 Other considerations For a complete overview of low power advantages please refer to the already mentioned AN4445. Following recommendations are specific to our case and example. 4.1 GPIO configuration Some GPIO settings may have great influence on power consumption while others do not. The pins used for the UART communication lines should be configured to their alternate function mode. It is not recommended to activate pull-ups if lowest possible power consumption is the most important goal, however, in some applications it may be necessary to improve the communication reliability. The speed setting has no consequences regarding the power consumption. Half-duplex mode, where applicable, may also lead to further power savings, however this configuration is not addressed in this document. Other pins, unused by the application, should be configured as analog inputs. The developer should not forget to put the debug lines also to analog, once the application is ready for deployment. 4.2 Clock configuration For LPUART peripheral clock, LSE source is the choice to reach 9600 baud with wakeup from Stop mode. For system clock, in order to keep the power consumption low, try to avoid using the PLL. Refer to the product datasheet for typical power consumptions for different clock configurations. 4.2.1 Clock prescalers The RCC module offers the possibility to tune down peripheral bus clocks, the AHB and APB frequency (RCC_CFGR register). Slowing the AHB brings significant power savings but in most cases it is not worth using. The memory interface is also clocked with AHB. While power consumption with prescaler of 8 drops by approximately 50%, the processing capability of the system drops even more Table 3. Clock options Source Advantages Limitations HSI Ready to use high speed clock Worst MHz / W ratio option MSI Easy and fast clock throttling from 65 kHz to 4.2 MHz Lowest overall power consumption when clocked below 1 MHz Clock is relatively unstable and imprecise HSE Potentially most power efficient at 1 MHz and above. Needs additional external component |
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