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AN4635 数据表(PDF) 22 Page - STMicroelectronics |
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AN4635 数据表(HTML) 22 Page - STMicroelectronics |
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22 / 34 page ![]() Power consumption comparison AN4635 22/34 DocID027290 Rev 1 6.7 Different peripheral clock settings DMA based communication was measured on three different APB clock divider settings, as shown in Figure 8, where the black line represents current consumption with no divider, the purple and green lines with divider set to 4 and to 8, respectively. Test with divider set to 16 is not included in the picture, as it would be difficult to distinguish it from the green one (and the power savings are even more marginal in comparison). Table 9. Configurations - AHB divider Curve in Figure 7 Black Green Red Idle mode between transmissions Stop JTAG interface OFF Current average over phases 2, 3 and 4 16.69 µA 9.75 µA 14.06 µA Clock 1 MHz MSI 250 kHz MSI 1 MHz MSI Voltage regulator Range 3 AHB/APB ratio 1/1 4/1 ULP/FWU +/+ Baud rate 9600 SW used Blocking operation (Com Polling) with RXSLEEP and TXSLEEP defined |
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