LTC1753_15 datasheet(7/24 Pages) LINER

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LTC1753

1753fa

COMP (Pin 10): External Compensation. The COMP pin is

connected directly to the output of the error amplifier and

the input of the PWM comparator. An RC + C network is

used at this node to compensate the feedback loop to

provide optimum transient response.

VFB (Pin 11): Voltage Feedback. VFB is the tap point of the

internal resistor divider connected from SENSE to SGND.

During rapid and heavy output loading conditions, a small

capacitor between the SENSE and VFB pin creates a feed-

forward path that reduces the transient recovery time. For

applications where extremely low output ripple is re-

quired, low ESR capacitors are typically used. In this case,

a small capacitor between SENSE and VFB helps to com-

pensate the switching loop. This pin can be left floating,

but should be isolated from high current switching nodes.

FAULT (Pin 12): Overvoltage Fault. FAULT is an open-

drain output. If VOUT reaches 13% above the nominal

output voltage, FAULT will go low and G1 and G2 will be

disabled. Once triggered, the LTC1753 will remain in this

state until the power supply is recycled or the OUTEN pin

is toggled. If OUTEN = 0, FAULT floats or is pulled high by

an external resistor.

PWRGD (Pin 13): Power Good. This is an open-drain

signal to indicate validity of output voltage. A high indi-

cates that the output has settled to within

±3% of the rated

output for more than 1ms. PWRGD will go low if the output

is out of regulation for more than 500

µs. If OUTEN = 0,

PWRGD pulls low.

VID0, VID1, VID2, VID3, VID4 (Pins 18, 17, 16, 15, 14):

Digital Voltage Select. TTL inputs used to set the regulated

output voltage required by the processor (Table 2). There

is an internal 20k

Ω pull-up at each pin. When all five VIDn

pins are high or floating, the chip will shut down.

OUTEN (Pin 19): Output Enable. TTL input which enables

the output voltage. The external MOSFET temperature can

be monitored with an external thermistor as shown in

Figure 11. When the OUTEN input voltage drops below

1.7V, the drivers are internally disabled to prevent the

MOSFETs from heating further. If OUTEN is less than 1.2V

for longer than 30

µs, the LTC1753 will enter shutdown

mode. The internal oscillator can be synchronized to a

faster external clock by applying the external clocking

signal to the OUTEN pin. (See Applications Information.)

G1 (Pin 20): Gate Drive for the Upper N-Channel MOSFET,

Q1. This output will swing from PVCC to GND. It will always

be low when G2 is high or the output is disabled.

PI FU CTIO S

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