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LTC1753

1753fa

LAYOUT CONSIDERATIONS

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1753. These items are also illustrated graphically in

the layout diagram of Figure 10. The thicker lines show the

high current paths. Note that at 10A current levels or

above, current density in the PC board itself is a serious

concern. Traces carrying high current should be as wide

as possible. For example, a PCB fabricated with 2oz

copper requires a minimum trace width of 0.15

" to

carry 10A.

1. In general, layout should begin with the location of the

power devices. Be sure to orient the power circuitry so

that a clean power flow path is achieved. Conductor

widths should be maximized and lengths minimized.

After you are satisfied with the power path, the control

circuitry should be laid out. It is much easier to find

routes for the relatively small traces in the control

circuits than it is to find circuitous routes for high

current paths.

2. The GND and SGND pins should be shorted directly at

the LTC1753. This helps to minimize internal ground

disturbances in the LTC1753 and prevents differences

in ground potential from disrupting internal circuit

operation. This connection should then tie into the

ground plane at a single point, preferably at a fairly quiet

point in the circuit such as close to the output capaci-

tors. This is not always practical, however, due to

physical constraints. Another reasonably good point to

make this connection is between the output capacitors

and the source connection of the low side FET Q2. Do

not tie this single point ground in the trace run between

the low side FET source and the input capacitor ground,

as this area of the ground plane will be very noisy.

3. The small signal resistors and capacitors for frequency

compensation and soft-start should be located very

close to their respective pins and the ground ends

connected to the signal ground pin through a separate

trace. Do not connect these parts to the ground plane!

4. The VCC and PVCC decoupling capacitors should be as

close to the LTC1753 as possible. The 10

µF bypass

capacitors shown at VCC and PVCC will help provide

optimum regulation performance.

5. The (+) plate of CIN should be connected as close as

possible to the drain of the upper MOSFET. An addi-

tional 1

µF ceramic capacitor between VIN and power

ground is recommended.

6. The SENSE and VFB pins are very sensitive to pickup

from the switching node. Care should be taken to isolate

SENSE and VFB from possible capacitive coupling to the

inductor switching signal. A 1

µF is required between

the SENSE pin and the SGND pin next to the LTC1753.

If PWRGD or FAULT are in the wrong logic state for

nonobvious reasons, check the layout of the SENSE and

VFB traces carefully. The 1µF capacitor should be

mounted as close to the SENSE pin as possible. In

addition, if feedforward compensation is in use, a

resistor in series with the feedforward capacitor might

be required. Finally, a low value resistor may be placed

between the output voltage and the SENSE pin (and the

µF capacitor). This RC will help filter high frequency

spikes.

7. OUTEN is a high impedance input and should be

externally pulled up to a logic HIGH for normal

operation.

8. Kelvin sense IMAX and IFB at Q1’s drain and source pins.

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