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LTC1753

1753fa

possible. It should also be located as close as possible

above (or below) the power ground plane. Some of the

phase shift problem can be solved by taking the AC

feedback locally at the regulator output while still taking

the DC feedback at the point of load. This permits accurate

DC regulation while still maintaining reasonable phase

margin. This is done by connecting the top of phase lead

capacitor, C2, locally at the regulator output while con-

necting the SENSE pin to the load. The corner frequency

1/(2

π • R2 • C2) must be significantly less than the

resonant frequency of the parasitic inductance and the

output capacitance 1/(2

π • √LDIST • CLOAD). Certain board

layouts may require RC2, a small series resistor, to de-

crease the slew rate of the feedforward path. In general, an

empirical approach to compensating this type of loop will

be best since it will be very difficult to estimate the parasitic

inductance of the power path analytically. It should be

noted that if the circuit can have a wide range of output

capacitance, this can be dangerous technique to employ

since the double-pole frequency will move as the load

capacitance changes. Be sure to verify stability with all

possible combinations of output capacitance.

VID0 to VID4, PWRGD and FAULT

The digital inputs (VID0 to VID4) program the internal DAC

which in turn controls the output voltage. These digital

input controls are intended to be static and are not

designed for high speed switching. Forcing VOUT to step

from a high to a low voltage by changing the VIDn pins

quickly can cause FAULT to trip.

Figure 9 shows the relationship between the VOUT voltage,

PWRGD and FAULT. To prevent PWRGD from interrupting

the CPU unnecessarily, the LTC1753 has a built-in tPWRBAD

delay to prevent noise at the SENSE pin from toggling

PWRGD. The internal time delay is designed to take about

500

µs for PWRGD to go low and 1ms for it to recover.

Once PWRGD goes low, the internal circuitry watches for

the output voltage to exceed 113% of the rated voltage. If

this happens, FAULT will be triggered. Once FAULT is

triggered, G1 and G2 will be forced low immediately and

the LTC1753 will remain in this state until VCC power

supply is recycled or OUTEN is toggled.

Figure 8. Feedback Connections for Remote Sense Applications

Figure 9. PWRGD and FAULT

RATED VOUT

VOUT

13%

–3%

tPWRBAD

tPWRGD

tFAULT

FAULT

PWRGD

1753 F09

DAC

LTC1753

1753 F08

ERR

RC2

SENSE

CLOAD

COUT

LDIST

VFB

LOAD

µF

COMP

APPLICATIO S I FOR ATIO

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