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LTC1753

1753fa

Figure 7b. Bode Plot of the LTC1753 Overall Transfer Function

Figure 7c. Bode Plot of the LTC1753 Overall Transfer Function

Using a Low ESR Output Capacitor

– 20dB/DECADE

fCO

fESR

FREQUENCY

1753 F07b

fSW = LTC1753 SWITCHING

FREQUENCY

fCO = CLOSED-LOOP CROSSOVER

FREQUENCY

fLC

poor load transient response despite the improvement in

output voltage ripple.

To resolve this problem, a small capacitor can be con-

nected between the SENSE and VFB pins to create a pole-

zero pair in the loop compensation. The zero location is

prior to the pole location and thus, phase lead can be

added to boost the phase margin at the loop crossover

frequency. The pole and zero locations are located at:

fZC2 =

and

π(R2)(C2)

fPC2 =

π(R12)(C2)

where R12 is the parallel combination resistance of R1 and

R2. Choose C2 so that the zero is located at a lower

frequency compared to fCO and the pole location is high

enough that the closed loop has enough phase margin for

stability. Figure 7c shows the Bode plot using phase lead

compensation around the LTC1753 internal resistor

divider network.

Although a mathematical approach to frequency compen-

sation can be used, the added complication of input and/

or output filters, unknown capacitor ESR, and gross

operating point changes with input voltage, load current

variations, all suggest a more practical empirical method.

This can be done by injecting a transient current at the load

and using an RC network box to iterate toward the final

compensation values, or by obtaining the optimum loop

The ESR of the output capacitor forms a zero at the

frequency:

fESR =

π(ESR)(COUT)

The compensation network at the error amplifier output is

to provide enough phase margin at the 0dB crossover

frequency for the overall closed-loop transfer function.

The zero and pole from the compensation network are:

fZ =

π(RC)(CC) and

fP =

π(RC)(C1) respectively.

Figure 7b shows the Bode plot of the overall transfer

function.

The compensation value used in this design is based on

the following criteria: fSW = 12fCO, fZ = fLC and fP = 5fCO. At

the loop crossover frequency fCO, the attenuation due the

LC filter and the input resistor divider is compensated by

the gain of the PWM modulator and the gain of the error

amplifier (gmERR)(RC).

When low ESR output capacitors (Sanyo OS-CON) are

used, the ESR zero can be high enough in frequency that

it provides little phase boost at the loop crossover fre-

quency. Therefore, inadequate phase margin is obtained

for the system. This causes loop stability problems and

– 20dB/DECADE

fCO

fZC2

fESR

fPC2

FREQUENCY

1753 F07c

fSW = LTC1753 SWITCHING

FREQUENCY

fCO = CLOSED-LOOP CROSSOVER

FREQUENCY

fLC

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