LTC1753_15 datasheet(6/24 Pages) LINER

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LTC1753

1753fa

Expanded View of Overshoot

Illustrates 0% Duty Cycle

Operation, VOUT = 2.8V

Expanded View of Undershoot

Illustrates 100% Duty Cycle

Operation, VOUT = 2.8V

VOUT

20mV/DIV

10V/DIV

µs/DIV

1753 G18

VOUT

20mV/DIV

10V/DIV

µs/DIV

1753 G19

the SENSE pin, the initial output voltage can be raised

slightly. Since the internal divider has a nominal imped-

ance of 108k

Ω, a 1100Ω series resistor will raise the

nominal output voltage by 1%. If an external resistor is

used, the value of the 1

µFcapacitorontheSENSEpinmust

be greatly reduced or loop phase margin will suffer. Set a

time constant for the RC combination of approximately

0.1

µs. So, for example, with a 1100Ω resistor, set

C = 90pF. Use a standard 100pF capacitor. In addition, LTC

recommends that the 1

µFcapacitorbeconnectedfromthe

top of the additional external resistor directly to SGND.

IMAX (Pin 7): Current Limit Threshold. Current limit is set

by the voltage drop across an external resistor connected

between the drain of Q1 and IMAX. There is a 190µA internal

pull-down at IMAX.

IFB (Pin 8): Current Limit Sense Pin. Connect to the

switching node between the source of Q1 and the drain of

Q2. If IFB drops below IMAX when G1 is on, the LTC1753

will go into current limit. The current limit circuit can be

disabled by floating IMAX and shorting IFB to VCC.

SS (Pin 9): Soft-Start. Connect to an external capacitor to

implement a soft-start function. During moderate over-

load conditions, the soft-start capacitor will be discharged

slowly in order to reduce the duty cycle. In hard current

limit, the soft-start capacitor will be forced low immedi-

ately and the LTC1753 will rerun a complete soft-start

cycle. CSS must be selected such that during power-up the

current through Q1 will not exceed the current limit value.

G2 (Pin 1): Gate Drive for the Lower N-Channel MOSFET,

Q2. This output will swing from PVCC to GND. It will always

be low when G1 is high or when the output is disabled. To

prevent undershoot during a soft-start cycle, G2 is held

low until G1 first goes high.

PVCC (Pin 2): Power Supply for G1 and G2. PVCC must be

connected to a potential of at least VIN + VGS(ON)Q1. For

normal applications, connect PVCC to a 12V power supply

or generate PVCC using a simple charge pump.

GND (Pin 3): Power Ground. GND should be connected to

a low impedance ground plane in close proximity to the

source of Q2.

SGND (Pin 4): Signal Ground. SGND is connected to the

low power internal circuitry and should be connected to

the negative terminal of the output capacitor where it

returns to the ground plane. GND and SGND should be

shorted directly at the LTC1753.

VCC (Pin 5): Power Supply. Power for the internal low

power circuity. VCC should be wired separately from the

drain of Q1 if they share the same supply. A 10

µF bypass

capacitor is recommended from this pin to SGND.

SENSE (Pin 6): Output Voltage Pin. Connect to the positive

terminal of the output capacitor. There is an internal 108k

resistor connected from this pin to SGND. SENSE is a very

sensitive pin; for optimum performance, connect an exter-

nal 1

µF capacitor from this pin to SGND. By connecting a

small external resistor between the output capacitor and

TYPICAL PERFOR A CE CHARACTERISTICS

PI FU CTIO S

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