DM385 datasheet(4/281 Pages) TI

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DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

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1.3

Description

DM385 and DM388 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power,

programmable platform that leverages TI’s DaVinci processor technology to meet the processing needs of

HD Video Conferencing - Skype endpoints, IP Netcam, Digital Signage, Media Players and Adapters,

Mobile Medical Imaging, Network Projectors, Home Audio and Video Equipment, and similar devices in

SD, HD, and 4K x 2K resolutions. The Programmable High-Definition Video Image Processor of the

device supports 1080p60 of real time H.264BP/MP/HP video encode or decode. The included best-in-

class H.264 encoder provides high-quality video encode for the lowest possible bit rate under all

conditions, reducing valuable storage space to a minimum. In addition, the device also supports other

video codecs such as MJPEG, MPEG-2, and MPEG-4. The device provides a full set of video

preprocessing and postprocessing functions to ensure the best video quality. The low power consumption

and high performance of the device makes it particularly suitable for portable and automotive applications.

The DM388 is uniquely capable of running the Fourth-Generation Motion-Compensated Noise Filtering

technology of TI.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs)

to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and

high processing performance through the maximum flexibility of a fully integrated mixed processor

solution. The device also combines programmable video and audio processing with a highly integrated

peripheral set.

The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load

many video and imaging processing tasks for common video and imaging algorithms. Programmability is

provided by an ARM Cortex-A8 RISC CPU with NEON extension and high-definition video and imaging

coprocessors. The ARM lets developers separate control functions from A/V algorithms programmed on

coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC

processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache;

256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each peripheral, see the related sections in this document and the

associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem;

Dual-Port Gigabit Ethernet MACs (10/100/1000 Mbps) (Ethernet Switch) with MII/RMII/GMII/RGMII and

MDIO interface supporting IEEE 1588 Time-Stamping, and Industrial Ethernet Protocols; two USB ports

with integrated 2.0 PHY; PCIe x1 GEN2-Compliant interface; two serializer McASP audio serial ports (with

DIT mode); three UARTs with IrDA and CIR support; four SPI serial interfaces; a CSI2 serial connection;

three MMC/SD/SDIO serial interfaces; four I2C master and slave interfaces; a parallel camera interface

(CAM); up to 125 general-purpose I/Os (GPIOs); eight 32-bit general-purpose timers; system watchdog

timer; DDR2/DDR3/DDR3L SDRAM interface; flexible 8- or 16-bit asynchronous memory interface; a Spin

Lock; and Mailbox.

Additionally, TI provides a complete set of development tools for the ARM which include C compilers and

a Microsoft® Windows® debugger interface for visibility into source code execution.

High-Performance System-on-Chip (SoC)

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Product Folder Links: DM385 DM388

DM385 数据表(PDF) 4 Page - Texas Instruments

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