DM385 datasheet(11/281 Pages) TI

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DM385, DM388

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SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

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CP15 System Control Coprocessor

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NEON 64-/128-bit Hybrid SIMD Engine for Multimedia

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Enhanced VFPv3 Floating-Point Coprocessor

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Enhanced Memory Management Unit (MMU)

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Separate Level-1 Instruction and Data Caches

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Integrated Level-2 Cache with ECC Support

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128-bit Interconnect with Level 3 Fast (L3) System Memories and Peripherals

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Embedded Trace Module (ETM).

2.4.2

Embedded Trace Module (ETM)

To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an

embedded trace module (ETM). The ETM consists of two parts:

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The Trace port which provides real-time trace capability for the ARM Cortex-A8.

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Triggering facilities that provide trigger resources, which include address and data comparators,

counter, and sequencers.

The ARM Cortex-A8 trace port is not pinned out and is, instead, only connected to the system-level

Embedded Trace Buffer (ETB). The ETB has a 32KB buffer memory. ETB enabled debug tools are

required to read/interpret the captured trace data.

2.4.3

ARM Cortex-A8 Interrupt Controller (AINTC)

The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests

from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor.

2.4.4

ARM Cortex-A8 PLL (PLL_ARM)

The ARM Cortex-A8 subsystem contains an embedded PLL Controller (PLL_ARM) for generating the

subsystem’s clocks from the device Clock input.

2.4.5

ARM Processor Interconnect

The ARM Cortex-A8 processor is connected through the arbiter to the L3 interconnect port. The L3

interconnect port is 128-bits wide and provides access to the other device modules.

Device Overview

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