DM385 datasheet(70/281 Pages) TI

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DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

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Table 3-16. DDR2/DDR3/DDR3L Memory Controller 0 Terminal Functions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

DDR[0]_D[21]

DDR[0] Data Bus

I/O

AG16

DDR[0]_D[22]

DDR[0] Data Bus

I/O

AD16

DDR[0]_D[23]

DDR[0] Data Bus

I/O

AC16

DDR[0]_D[24]

DDR[0] Data Bus

I/O

AK19

DDR[0]_D[25]

DDR[0] Data Bus

I/O

AJ19

DDR[0]_D[26]

DDR[0] Data Bus

I/O

AH19

DDR[0]_D[27]

DDR[0] Data Bus

I/O

AF19

DDR[0]_D[28]

DDR[0] Data Bus

I/O

AD19

DDR[0]_D[29]

DDR[0] Data Bus

I/O

AC19

DDR[0]_D[30]

DDR[0] Data Bus

I/O

AJ20

DDR[0]_D[31]

DDR[0] Data Bus

I/O

AG20

DDR[0]_DQM[0]

Data Mask for lower byte data bus DDR[0]_D[7:0]

AL8

DDR[0]_DQM[1]

Data Mask for DDR[0]_D[15:8]

AK12

DDR[0]_DQM[2]

Data Mask for DDR[0]_D[23:16]

AJ15

DDR[0]_DQM[3]

Data Mask for upper byte data bus DDR[0]_D[31:24]

AK18

DDR[0]_DQS[0]

Data Strobe for lower byte data bus DDR[0]_D[7:0]

I/O

AL11

DDR[0]_DQS[0]

Complimentary data strobe for lower byte data bus

I/O

AK11

DDR[0]_D[7:0]

DDR[0]_DQS[1]

Complimentary data strobe for DDR[0]_D[15:8]

I/O

AK15

DDR[0]_DQS[1]

Data Strobe for DDR[0]_D[15:8]

I/O

AL15

DDR[0]_DQS[2]

Data Strobe for DDR[0]_D[23:16]

I/O

AL17

DDR[0]_DQS[2]

Complimentary data strobe for DDR[0]_D[23:16]

I/O

AK17

DDR[0]_DQS[3]

Complimentary data strobe for upper byte data bus

I/O

AK20

DDR[0]_D[31:24]

DDR[0]_DQS[3]

Data Strobe for upper byte data bus DDR[0]_D[31:24]

I/O

AL20

DDR[0]_ODT[0]

DDR[0] On-Die Termination for Chip Select 0

AL21

DDR[0]_RAS

DDR[0] Row Address Strobe output

AJ25

DDR[0]_RST

DDR[0] Reset output

AA20

DDR[0]_VTP

DDR VTP Compensation Resistor Connection

AL30

DDR[0]_WE

DDR[0] Write Enable

AL26

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