DM385 datasheet(85/281 Pages) TI

85 / 281 page

DM385, DM388

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SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

3.3.15 PCI Express (PCIe)

Table 3-33. PCI Express (PCIe) Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

PCIE_RXN0

PCIE Receive Data Lane 0. When the PCIe SERDES are I

J30

powered down, these pins should be left unconnected.

PCIE_RXP0

PCIE Receive Data Lane 0. When the PCIe SERDES are I

K30

powered down, these pins should be left unconnected.

PCIE_TXN0

PCIE Transmit Data Lane 0. When the PCIe SERDES

K31

are powered down, these pins should be left

unconnected.

PCIE_TXP0

PCIE Transmit Data Lane 0. When the PCIe SERDES

L31

are powered down, these pins should be left

unconnected.

SERDES_CLKN

PCIE Serdes Reference Clock Inputs. When PCIe is not

H31

used these pins can be left unconnected.

SERDES_CLKP

PCIE Serdes Reference Clock Inputs. When PCIe is not

H30

used these pins can be left unconnected.

NOTE

PCIe is supported on all DM385 devices and also on DM388 devices with PCIe enabled. For

DM388 devices with PCIe disabled, the pins in Table 3-33 should be left unconnected.

Device Pins

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