DM385 datasheet(109/281 Pages) TI

109 / 281 page

DM385, DM388

www.ti.com

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

Table 4-1. Boot Mode Order

BTMODE[4:0]

1st

2nd

3rd

4th

00000

RESERVED

00001

UART

XIP w/WAIT (MUX0)(1)(2)

MMC

SPI

00010

UART

SPI

NAND

NANDI2C

00011

UART

SPI

XIP (MUX0)(1)(2)

MMC

00100

EMAC(3)

SPI

NAND

NANDI2C

00101

RESERVED

00110

RESERVED

00111

EMAC(3)

MMC

SPI

XIP (MUX1)(1)(2)

01000

PCIE_32(4)

RESERVED

01001

PCIE_64(4)

RESERVED

01010

RESERVED

01011

RESERVED

01100

RESERVED

01101

RESERVED

01110

RESERVED

01111

Fast XIP (MUX0)(1)

UART

EMAC(3)

PCIE_64(4)

10000

XIP (MUX1)(1)(2)

UART

EMAC(3)

MMC

10001

XIP w/WAIT (MUX1)(1)(2)

UART

EMAC(3)

MMC

10010

NAND

NANDI2C

SPI

UART

10011

NAND

NANDI2C

MMC

UART

10100

NAND

NANDI2C

SPI

EMAC(3)

10101

NANDI2C

MMC

EMAC(3)

UART

10110

SPI

MMC

UART

EMAC(3)

10111

MMC

SPI

UART

EMAC(3)

11000

SPI

MMC

PCIE_32(4)

RESERVED

11001

SPI

MMC

PCIE_64(4)

RESERVED

11010

XIP (MUX0)(1)(2)

UART

SPI

MMC

11011

XIP w/WAIT (MUX0)(1)(2)

UART

SPI

MMC

11100

RESERVED

11101

RESERVED

11110

RESERVED

11111

Fast XIP (MUX0)(1)

EMAC(3)

UART

PCIE_32(4)

(1)

GPMC CS0 eXecute In Place (XIP) boot for NOR/OneNAND/ROM. MUX0/1 refers to the multiplexing option for the GPMC_A[12:0] pins.

For more detailed information on booting the device, including which pins are used for each boot mode, see the ROM Code Memory

and Peripheral Booting chapter in the device-specific Technical Reference Manual.

(2)

When the XIP (MUX0), XIP (MUX1), XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode is selected, the sampled value from

BTMODE[10] pin is used to select between GPMC pin configuration options shown in Table 4-2, XIP (on GPMC) Boot Options.

(3)

When the EMAC bootmode is selected, the sampled value from BTMODE[9:8] pins are used to determine the Ethernet PHY Mode

Selection (see Table 4-7).

(4)

When the PCIe bootmode is selected (PCIE_32 or PCI_64), the sampled value from BTMODE[15:12] pins are used to determine the

addressing options. For more detailed information on the PCIe addressing options, see the ROM Code Memory and Peripheral Booting

chapter in the device-specific Technical Reference Manual.

4.2.1

XIP (NOR) Boot Options

Table 4-2 shows the XIP (NOR) boot mode GPMC pin configuration options (Option A: BTMODE[10] = 0

and Option B: BTMODE[10] = 1). For Option B, the pull state on select pins is reconfigured to IPD and

remains IPD after boot until the user software reconfigures it. In Table 4-2, GPMC_A[1:12] are configured

only for Non-Muxed NOR flash. In the case of Muxed NOR Flash, GPMC_D[15:0] act as both address and

data lines so configuration of GPMC_A[1:12] in XIP_Mux0 mode and XIP_Mux1 mode doesn't apply for a

Muxed NOR flash and those pins are not configured by Boot ROM.

Device Configurations

109

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