DM385 datasheet(141/281 Pages) TI

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DM385, DM388

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SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

•

Power-On Reset (asserted after the BTMODE[11] pin is latched)

•

External Warm Reset (asserted after the BTMODE[11] pin is latched)

•

Emulation Warm Reset

•

Software Global Cold/Warm Reset

The RSTOUT_WD_OUT pin remains asserted until the PRCM releases the host ARM Cortex-A8

processor for reset.

7.3.15 Effect of Reset on Emulation & Trace

The device Emulation & Trace Logic will only be reset by the following sources:

•

Power-On Reset

•

Software Global Cold Reset

•

Test Reset

Other than these three reset types, none of the other resets will affect the Emulation and Trace Logic.

However, the multiplexing of the EMU[4:2] pins is reset by all system reset types except Test Reset.

7.3.16 Reset During Power Domain Switching

Each Power Domain has a dedicated Warm Reset and Cold Reset. Warm Reset for a Power Domain is

asserted under either of the following two conditions:

1. An External Warm Reset, Emulation Warm Reset, or Software Global Warm Reset occurs

2. When that Power Domain switches from the "ON" state to the "OFF" state

Cold Reset for a Power Domain is asserted under either of the following two conditions:

1. Power-On Reset or Software Global Cold Reset occurs

2. When that Power Domain switches from the "OFF" state to the "ON" state

7.3.17 Pin Behaviors at Reset

When any reset, other than Test Reset, (all described in Section 7.3.1, System-Level Reset Sources) is

asserted, all device I/O pins are reset into a Hi-Z state except for:

•

Emulation Pins. These pins are only put into a Hi-Z state when Test Reset (TRST) is asserted.

•

EMAC Switch Pins. These pins are always put into a Hi-Z state during Power-On Reset. However,

some EMAC Switch pins will not be put into a Hi-Z state during the other reset modes when the

ISO_CONTROL bit in the RESET_ISO register of the Control Module is programmed as a "1". For

more details, see the description of the RESET_ISO register in the Control Module chapter in the

device-specific Technical Reference Manual.

•

RSTOUT_WD_OUT Pin during any reset types except for POR and RESET. For more detailed

information on RSTOUT_WD_OUT pin behavior, see Section 7.3.14, RSTOUT_WD_OUT Pin.

•

DDR[0] Address/Control Pins (CLK, CLK, CKE, WE, CS[0], RAS, CAS, ODT[0], RST, BA[2:0], A[15:0]).

These pins are 3-stated during reset. However, these pins are then driven to the same value as their

internal pull resistor reset value when reset is released.

In addition, the PINCNTL registers, which control pin multiplexing, enabling the IPUs/IPDs, and enabling

the receiver, are reset to their default state. Again, enabling the EMAC Switch reset isolation prevents

some PINCNTL registers from being reset.

For details on EMAC Switch reset isolation, see the descriptions of the RESET_ISO register and the

PINCNTL registers in the Control Module chapter in the device-specific Technical Reference Manual.

Internal pull-up/down (IPU/IPD) resistors are enabled during and immediately after reset as described in

Section 3.3, Terminal Functions of this document.

Power, Reset, Clocking, and Interrupts

141

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