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AS0260CSSC28SUD20 数据表(PDF) 79 Page - ON Semiconductor |
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AS0260CSSC28SUD20 数据表(HTML) 79 Page - ON Semiconductor |
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79 / 83 page  AS0260 DS Rev. G Pub. 5/15 EN 79 ©Semiconductor Components Industries, LLC, 2015. AS0260: 1/6-Inch 1080P High-Definition (HD) System-On-A-Chip (SOC) Digi- tal Image Sensor Table 27: Two-Wire Serial Interface Timing Data fEXTCLK = 24 MHz; REG_IN0 = 1.8V; VDD_IO = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; T J = 70°C; CLOAD = 68.5pF Figure 45: Two-Wire Serial Bus Timing Parameters Symbol Parameter Conditions Min Typ Max Unit fSCLK Serial interface input clock frequency 100 – 400 kHz tSCLK Serial interface input clock period 2.5 – 10 s SCLK duty cycle 45 50 55 % tr SCLK/SDATA rise time – – 300 ns tSRTS Start setup time Master write to slave 600 – – tSRTH Start hold time Master write to slave 300 – – ns tSDH SDATA hold Master write to slave 300 – – ns tSDS SDATA setup Master write to slave 300 – – ns tSHAW SDATA hold to ack Master read from slave 150 – – ns tAHSW Ack hold to SDATA Master read from slave 150 – – ns tSTPS Stop setup time Master write to slave 300 – – ns tSTPH Stop hold time Master write to slave 600 – – ns tSHAR SDATA hold to ack Master write to slave 300 – – ns tAHSR Ack hold to SDATA Master write to slave 300 – – ns tSDHR SDATA hold Master read from slave 300 – – ns tSDSR SDATA setup Master read from slave 350 – – ns SCLK SDATA SCLK SDATA Write Start Ack Read Start Ack t SHAR t AHSR t SDHR t SDSR Read Sequence Write Sequence Read Address Bit 7 Read Address Bit 0 Register Value Bit 7 Register Value Bit 0 Write Address Bit 7 Write Address Bit 0 Register Value Bit 7 Register Value Bit 0 t SRTS t SCLK t SDH t SDS t SHAW t AHSW Stop t STPS t STPH t SRTH Ack |
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