7 6 5 4 3 2 1 0

BT: Borrow Toggle flip-flop.

Toggles every time CNTR underflows.

CT: Carry toggle flip-flop.

Toggles every time CNTR overflows.

CPT: Compare toggle flip-flop.

Toggles every time PR equals CNTR.

S: Sign flag. Set to 1 when CNTR underflows.

Reset to 0 when CNTR overflows.

FLAG

E: Error latch. Set to 1 when parameter t4 or t5 is violated (see p.8 for t4 and t5)

Irrelevant in non-quadrature mode.

U/D: Up/Down flag. Set to 1 when counting up

and reset to 0 when counting down.

Not used. Always reset to 0.

IDX: Index. Set to 1 when designated index input transitions to active level.

0

Filter Clock Prescalers: XPSC and YPSC

Each PSC is an 8-bit programmable modulo-n down counter, driven by the FCK input. The division factor n is stored

into each PSC from its associated PR register low byte, PR0. The PSCs provide the ability to generate independent

filter

clock frequencies for each channel used for filtering the quadrature clocks applied at the A and B inputs in

quadrature mode.The same filter clocks are also used for filtering the designated INDEX inputs.

T

he effective internal filter

frequency at the FCK input. For proper operation the required condition is:

is the frequency at A (or B) input. The FCK pin is not used in non-quadrature mode and

7267-091615-2

Flag Register: XFLAG and YFLAG

The FLAG registers hold the status information of the CNTRs and can be read on the data bus. All bits excepting

the E and the IDX bits change dynamically to represent the instantaneous status of the CNTR's. In contrast the E

and the IDX bits are latched. Once set they can only be reset via the RLD registers.

7 6 5 4 3 2 1 0

0: NOP

0

1

0

RLD

1: Reset BP

0

0

1

0

1

1

0

0

: Select the RLD addressed by X/Y input

1

: Select both XRLD and YRLD together

(Note: D7 = 1 overrides X/Y input)

: Select RLD

: NOP

: Reset CNTR

: Reset BT, CT, CPT,S, IDX

: Reset E

0

0

1

0

0

1

1

1

: NOP

: Transfer PR to CNTR

(Note: All 24-bits are transferred in parallel)

: Transfer CNTR to OL

(Note: All 24-bits are transferred in parallel)

: Transfer PR0 to PSC

Reset and Load Signal Decoders: XRLD and YRLD

Following functions can be performed by writing a control byte into an RLD: Transfer PR to CNTR, Transfer

CNTR to OL, reset CNTR, reset FLAG and reset BP

.

: