24-BIT DUAL-AXIS QUADRATURE COUNTER

LS7267 Registers:

LS7267 has a set of registers associated with each X and Y axis. All X-axis registers have the name prefix X,

whereas all Y-axis registers have the prefix Y. Selection of a specific register for Read/Write is made from the decode

of the three most significant bits (D7 - D5) of the data-bus. CS input enables the IC for Read/Write. C/D input selects

between control and data information for Read/Write. Following is a complete list of LS7267 registers.

OCT 2015

7267-102215-1

PIN ASSIGNMENT

TOP VIEW

Preset Registers: XPR and YPR

Each of these PRs are 24-bit wide. 24-bit data can be written into a PR, one byte at a time, in a sequence of three data

write cycles.

7

7

0

0 7

0

HI BYTE

MID BYTE

LO BYTE

PR

(PR2)

(PR1)

(PR0)

Output Latches: XOL and YOL

Each OL is 24-bits wide. In effect, the OLs are the output ports for the CNTRs. Data from each CNTR can be loaded

into its associated OL and then read back on the data-bus, one byte at a time, in a sequence of three data Read

cycles.

7

7

0

0 7

0

HI BYTE

MID BYTE

LO BYTE

OL

(OL2)

(OL1)

(OL0)

Counters: XCNTR and YCNTR

Each of these CNTRs are 24-bit synchronous Up/Down counters. The count clocks for each CNTR is derived from its

associated A/B inputs. Each CNTR can be loaded with the content of its associated PR.

Byte Pointers: XBP and YBP

The Read and Write operations on an OL or a PR always accesses one byte at a time. The byte that is accessed is

addressed by one of the BPs. At the end of every data Read or Write cycle on an OL or a PR, the associated BP is

automatically incremented to address the next byte.

FEATURES:

• Up to 50MHz count frequency in non-quadrature mode;

x4 quadrature mode.

• Dual 24-bit counters to support X and Y axes in

motion control applications. • Dual 24-bit comparators.

• Digital filtering of the input quadrature clocks

• Programmable 8-bit separate filter clock prescalers

for each axis.

• Error flags for noise exceeding filter band width.

• Programmable Index Input and other programmable I/Os.

• Independent mode programmability for each axis.

• Programmable count modes:

Quadrature (x1, x2, x4) / Non-quadrature,

Normal / Modulo-N / Range Limit / Non-Recycle,

Binary / BCD.

• 8-bit 3-State data I/O bus.

• TTL/CMOS compatible I/Os.

•

LS7267 (DIP); LS7267-S (SOIC); LS7267-TS (TSSOP)

LSI/CSI

LS7267

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405

UL

®

A3800

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

YLCNTR/YLOL

FCK

D0

D1

D2

D3

D4

D5

D6

D7

C/D

WR

CS

RD

XRCNTR/XABG

XLCNTR/XLOL

XA

XB

XFLG1

YA

YB

YFLG2

YFLG1

YRCNTR/YABG

XFLG2

X/Y