Input/Output Control Register: XIOR and YIOR

The functional modes of the programmable input and output pins are configured by writing into the IORs.

7267-112612-4

INDEX CONTROL REGISTERS: XIDR and YIDR

Either the LCNTR/LOL or the RCNTR/ABG inputs can be initialized to operate in the INDEX mode. In the

INDEX mode

the index signal from an encoder, applied to one of the two inputs performs either reset_CNTR,

Load_CNTR or Load_OL operation synchronously with the quadrature clocks, the internal load or reset signal

being generated at the same angular orientation of the encoder in both CW and CCW directions. In contrast in

non-INDEX mode these signals are applied

The index mode is unconditionally disabled in non-quadrature mode.

7 6 5 4 3 2 1 0

0: Disable Index

0: Negative Index Polarity

0: LCNTR/LOL pin in index mode (See Note 1)

IDR

1: Enable Index

1: Positive Index Polarity

1: RCNTR/ABG pin in index mode (See Note 2)

1

1

0: Select IDR addressed by X/Y input

Not used

: Select IDR

1: Select both XIDR and YIDR (Note: D7=1 overrides X/Y input)

Note 1: Function selected for this pin via IOR, becomes the operating INDEX functio

n.

Note 2: RCNTR/ABG input must also be initialized as the reset

_CNTR input via IOR

:

mode

Note 3:

“Enable Index mode” causes the synchronous mode for the selected input (Pin 1, 18, 19 and 28)

to be enabled. “Disable Index mode” causes the asynchronous mode for the selected pin to be enabled.

The input, however, is not disabled in either configuration.

mode

7 6 5 4 3 2 1 0

0 : Disable inputs A and B

0 : LCNTR/LOL pin is Load CNTR input

0 : RCNTR/ABG pin is Reset CNTR input

0

IOR

1 : Enable inputs A and B

1 : LCNTR/LOL pin is Load OL input

1 : RCNTR/ABG pin is A and B Enable gate

0

0

: FLG1 pin is COMPARE output; FLG2 pin is BORROW output

1

: FLG1 pin is CARRY output; FLG2 pin is BORROW output

: FLG1 pin is Carry/Borrow output and FLG2 pin is U/D (FLAG register bit 5)

: FLG1 is INDX (low pulse at INDEX pin active level); FLG2 is E (FLAG register bit 4)

(For FLG1 to output INDX, IDR bit0 must be set to 1)

0: Select IOR addressed by X/Y input

1: Select both XIOR and YIOR together (Note: D7=1 overrides X/Y input)

: Select IOR

1

1

1

0

1

0