UP

DOWN

A

B

X4_CLK

X2_CLK

CNTR advances

X1_CLK

Fig 4. A/B quadrature clocks and internal count clocks in X1, X2 and X4 modes

UP

DOWN

A

B

INDEX

tidx

X4_CLK

CNTR

fffffd

fffffe ffffff

0

1

2

3

2

1

0

ffffff fffffe fffffd

INDX (FLG1)

CY/ (FLG1)

BW/ (FLG2)

CMP/ (FLG1

Note. CMP/ signal is arbitrarily shown to be generated at CNTR = fffffe

Note. In modulo-N and range-limit modes the CMP/ output is generated in up count only

Note. INDEX signal must overlap quarter cycle of both A and B high or both A and B low. Shown here both low.

Fig 5. FLG1 and FLG2 outputs in quadrature count mode

7267-052815-11

tQ3

tQ3

tQ3

tQ3

thi

tsi