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LS7267 数据表(PDF) 8 Page - LSI Computer Systems

部件名 LS7267
功能描述  24-BIT DUAL-AXIS QUADRATURE COUNTER
PDF  15 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  LSI [LSI Computer Systems]
网页  http://www.lsicsi.com
标志 LSI - LSI Computer Systems

LS7267 数据表(HTML) 8 Page - LSI Computer Systems

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7267
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Transient Characteristics. (TA = -25˚C to +80˚C)
Parameter
Symbol Min. Value
Max.Value
Unit
Remarks
For VDD = 3V to 5.5V:
Read Cycle (See Fig. 1)
RD Pulse Width
tr1
80
-
ns
-
CS Set-up Time
tr2
80
-
ns
-
CS Hold Time
tr3
0
-
ns
-
C/D Set-up Time
tr4
80
-
ns
-
C/D Hold Time
tr5
10
-
ns
-
X/Y Set-up Time
tr6
80
-
ns
-
X/Y Hold Time
tr7
10
-
ns
-
Data Bus Access Time
tr8
80
-
ns
Access starts when both RD
and CS are low.
Data Bus Release Time
tr9
-
35
ns
Release starts when either RD
or CS is terminated.
Back to Back Read delay
tr10
90
-
ns
-
Write Cycle (See Fig. 2)
WR Pulse Width
tW1
45
-
ns
-
CS Set-up Time
tW2
45
-
ns
-
CS Hold Time
tW3
0
-
ns
-
C/D Set-up Time
tW4
45
-
ns
-
C/D Hold Time
tW5
10
-
ns
-
X/Y Set-up Time
tW6
45
-
ns
-
X/Y Hold Time
tW7
10
-
ns
-
Data Bus Set-up Time
tW8
45
-
ns
-
Data Bus Hold Time
tW9
10
-
ns
-
Back to Back Write Delay
tW10
90
-
ns
-
Load CNTR, Reset CNTR and
Load OL Pulse Width
t11
35
-
ns
-
For VDD = 3V:
Quadrature Mode (See Fig. 3-5)
FCK High Pulse Width
t1
18
-
ns
-
FCK Low Pulse Width
t2
1
8
-
ns
-
FCK Frequency
fFCK
-
27
MHz
-
Mod-n Filter Clock(FCKn)Period
t3
36
-
ns
t3 = (n+1) (t1+t2),
where n = PSC = 0 to FFH
FCKn frequency
fFCKn
-
27
MHz
-
Quadrature Separation
t4
40
-
ns
t4 > t3
Quadrature Clock Pulse Width
t5
160
-
ns
t5 >4t3
Quadrature Clock frequency
fQA, fQB
-
3.1
MHz
fQA = fQB = 1/(2t5)
Quadrature Clock to Count Delay
tQ1
4
t3
5
t3
-
-
x1/x2/x4 Count Clock Pulse Width tQ2
36
-
ns
tQ2 = t3
Index Input Pulse Width
tidx
76
-
ns
tidx > 2t3
Index setup/hold time
tsi/thi
5
-
ns
-
INDX Output Width
tQ3
18
-
ns
tQ3 = (t3 - t2)
Carry/Borrow/Compare Output Width
tQ3
18
-
ns
tQ3 = (t3 - t2)
Non-Quadrature Mode (See Fig. 6-7)
Clock A - High Pulse Width
t6
18
-
ns
-
Clock A - Low Pulse Width
t7
18
-
ns
-
Direction Input B Set-up Time
tbS
20
-
ns
-
Direction Input B Hold Time
tbh
10
-
ns
-
Gate Input (ABG) Set-up Time
tGS
20
-
ns
-
Gate Input (ABG) Hold Time
tGH
1
0
-
ns
-
Clock Frequency
fA
-
27
MHz
fA
= (1/ (t6 + t7) )
Clock to Carry or Borrow Out Delay
t9
-
2
0
ns
-
Carry or Borrow Out Pulse Width
t10
18
-
ns
t10
= t7
Clock to Compare Out Delay
t12
-
30
ns
-



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