7267-0

91615-5

I/O pins:

Following is a description of all the input/output pins.

YLCNTR/YLOL/ (pin 1). Input. Programmable input in

the y-axis which can be configured with the YIOR

register to function as either LD_YCNTR or LD_YOL

input. LD_YCNTR causes the YPR to be loaded into

YCNTR when the input is at active level. LD_YOL

causes YCNTR to be loaded into YOL when the input is

at active level.

In quadrature mode the input can further be initialized

with the YIDR register to function in either INDEX mode

or non-INDEX mode. The INDEX mode allows for the

direct interface with the INDEX output of an incremental

encoder. In this mode the YLCNTR/YLOL/ input is

sampled with the filter clock derived from the FCK input

clock which is used for validating the quadrature clocks

as well

In the INDEX mode the YCLNTR/YLOL/ input can be

configured for either high or low active logic levels with

the YIDR. In the non-INDEX mode the active level is not

programmable and is unconditionally set to low active.

In the non-INDEX mode YCLNTR/YLOL/ input is not

sampled with the filter clock and can be applied

asynchronously with respect to YA and YB inputs. In

non-quadrature mode the YCLNTR/YLOL/ input is

unconditionally set to the non-INDEX mode.

FCK. (pin 2). Input. A clock applied at the FCK input is

used for generating filter clocks for both X and Y axes.

The filter clocks are used for validating the quadrature

clocks (at XA, XB, YA and YB inputs), and the INDEX

signal ( at XLCNTR/XLOL/ or XRCNTR/ or

YLCNTR/YLOL/ or YRCNTR in INDEX mode). The clock

at the FCK input is divided down separately by XPSC

and YPSC prescalers to generate the filter clock for each

axis. The prescaler output frequency is given by:

input and n = [XPSC] or [YPSC].

For proper operation in the quadrature mode the

following condition of frequencies must be satisfied:

XB or YA or YB input..

In non-quadrature mode the filter clock is not used and

the FCK input must be tied off to either VDD or VSS.

VDD (pin 3). Supply voltage positive rail. +3V to +5V.

D0 through D7 (pins 4 through 11). Inputs/Outputs. The

8-bit databus D0 through D7 is a 3-state portal for the

READ/WRITE operation in and of the device. The

databus is common to both axes. During a read

operation when both CS/ and RD/ inputs are low, the

content of either the OL or the FLAG register of the

selected axis is placed on databus. During a write

operation the content of the databus is written into the

selected register at the trailing edge of the WR/ pulse.

When CS/ is high the databus is disabled and placed in

the high impedance state.

VSS (pin 12). Supply voltage negative rail or GND.

D/C (pin 13). Input. This input selects between a control

register or a data register for read/write operation

according to Table 1. When low, a write operation

causes the content of the databus to be written into the

selected PR register. When high, a write causes the

databus to be written into the selected control register.

During a read operation, a low at the D/C input causes

the content of the selected OL to be output on the

databus while a high causes the content of the selected

FLAG register to be output on the databus.

WR/ (pin 14). Input. A low pulse at the WR/ input causes

the content of the databus to be written into the selected

register according to Table 1. The write operation is

completed at the trailing edge of the WR/ pulse.

CS/ (pin 15). Input. A low at the CS/ input enables the

device for read or write operations. When the CS/ input

is high the read and write operations are disabled and

the databus, D0-D7 is placed in the high impedance

state.

RD/ (pin 16). Input. A low at the RD/ input causes the

content of the selected register to be output on the

databus according to Table 1.

X/Y (pin 17). Input. Selects between X and Y axis for

read and write. A low at this input selects the X axis

while a high selects the Y axis.

XRCNTR/XABG (pin 18). Input. Programmable input in

the x-axis which can be configured with the XIOR

register to function as either R_XCNTR or E_XAB input.

R_XCNTR causes the XCNTR to be reset to 0 when the

input is in the active level. E_XAB causes the input to

function as the XA and XB enable/disable gate. In this

mode XA and XB become enabled when the

XRCNTR/XABG input is high and disabled when the

input is low,

In quadrature mode the input can further be initialized

with the XIDR register to function in either INDEX mode

or non-INDEX mode. In the INDEX mode the

XRCNTR/XABG is sampled with the filter clock derived

from the FCK input clock which is used for validating the

quadrature clocks as well.

When configured in the INDEX mode the

XRCNTR/XABG input must also be configured as

R_XCNTR to function correctly. In the INDEX mode the

XRCNTR/XABG input can be configured for either high

or low active logic levels for the R_XCNTR function via

the XIDR register. In the non-INDEX mode the active

level is not programmable and is unconditionally set to

low active for the R_XCNTR function.

In the non-INDEX mode XRCNTR/XABG input is not

sampled with the filter clock and can be applied