STA016 datasheet(16/43 Pages) STMICROELECTRONICS

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STA016A

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6.2.9

PLL_AUDIO_XDIV_176 :

Address : 0xE4 (228)

Type : RW - DEC

Software Reset : 2

Description :

This register must contain a XDIV value that enables

the audio PLL to generate a frequency of ofact*176

kHz for the PCMCK.See table 1, 2 & 3.

Default value at soft reset assume :

–ofact == 256

– external crystal provide a CRYCK running at

14.31818 MHz

6.2.10 PLL_AUDIO_MDIV_176 :

Address : 0xE5 (229)

Type : RW - DEC

Software Reset : 8

Description :

This register must contain a MDIV value that enables

the audio PLL to generate a frequency of ofact*176

kHz for the PCMCK.See table 1,2 & 3.

Default value at soft reset assume :

–ofact == 256

– external crystal provide a CRYCK running at

14.31818 MHz

6.3 PLL_SYSTEM_CONFIGURATION

registers description

6.3.1

PLL_SYSTEM_PEL_50 :

Address : 0xE6 (230)

Type : RW - DEC

Software Reset : 0

Description :

This register must contain a PEL value that enables

the system PLL to generate a frequency of 50 MHz

for the SYSCK. See table 4.

Default value at soft reset assume :

– external crystal provide a CRYCK running at

14.31818 MHz

6.3.2

PLL_SYSTEM_PEH_50 :

Address : 0xE7 (231)

Type : RW - DEC

Software Reset : 0

Description :

This register must contain a PEH value that enables

the system PLL to generate a frequency of 50 MHz

for the SYSCK. See table 4.

Default value at soft reset assume :

– external crystal provide a CRYCK running at

14.31818 MHz

6.3.3

PLL_SYSTEM_NDIV_50 :

Address : 0xE8 (232)

Type : RW - DEC

Software Reset : 0

Description :

This register must contain a NDIV value that enables

the system PLL to generate a frequency of 50 MHz

for the SYSCK. See table 4.

Default value at soft reset assume :

– external crystal provide a CRYCK running at

14.31818 MHz

6.3.4

PLL_SYSTEM_XDIV_50 :

Address : 0xE9 (233)

Type : RW - DEC

Software Reset : 1

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