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STA016 数据表(PDF) 22 Page - STMicroelectronics

部件名 STA016
功能描述  MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY
PDF  43 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA016 数据表(HTML) 22 Page - STMicroelectronics

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Table 20. .
6.7.4
I_AUDIO_CONFIG_3 :
Address : 0x5D (93)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_4 register description..
6.7.5
I_AUDIO_CONFIG_4 :
Address : 0x5E (94)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
urate LR clocks (CD_LRCK & BS_LRCK) of CD & BS
input interfaces in audio mode.
Table 21.
6.7.6
I_AUDIO_CONFIG_5:
Address : 0x5F (95)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description.
6.7.7
I_AUDIO_CONFIG_6 :
Address : 0x60 (96)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description..
6.7.8
I_AUDIO_CONFIG_7 :
Address : 0x61 (97)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description..
Bit
Comment
CF8
Relative synchro :
0 : synchro with first data bit
1 : synchro one bit before first data bit
CF9
Data reception configuration :
0 : LSB first
1 : MSB first
CF10
Arithmetic type of the reception :
0 : unsigned data
1 : signed data
CF11
Bit to select the reference clock used to
generate BCK if clocks are in output
(CF2=1 & CF5=1). Otherwise this bit is
useless.
0 : SYSCK
1 : PCMCK
CF12
Reserved : to be set to 1
CF13
Reserved : to be set to 1
CF14
Reserved : to be set to 0
CF15
Reserved : to be set to 0
b7
b6
b5
b4
b3
b2
b1
b0
LR7
LR6
LR5
LR4
LR3
LR2
LR1
LR0
b7
b6
b5
b4
b3
b2
b1
b0
LR15 LR14 LR13 LR12 LR11 LR10
LR9
LR8
Bit fields
Comment
LR[5:0]
Length-1 of phase 1 of LR clocks
CD_LRCK & BS_LRCK.
Max value is 31.
LR[11:6]
Length-1 of phase 2 of LR clocks
CD_LRCK & BS_LRCK.
Max value is 31.
LR[15:12]
Reserved : to be set to 0
b7
b6
b5
b4
b3
b2
b1
b0
MA7MA6
MA5MA4
MA3MA2
MA1MA0
b7
b6
b5
b4
b3
b2
b1
b0
MA1
5
MA1
4
MA1
3
MA1
2
MA1
1
MA1
0
MA9
MA8
b7
b6
b5
b4
b3
b2
b1
b0
MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16



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