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STA016 数据表(PDF) 20 Page - STMicroelectronics |
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STA016 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 43 page ![]() STA016A 20/43 6.6.2 I_AUDIO_CONFIG_1: Address : 0x5B (91) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, this register configure the I2Sin interface Table 16. . Table 17. 6.6.3 I_AUDIO_CONFIG_2 : Address : 0x5C (92) Type : RW - DEC Software Reset : 0 Description : See I_AUDIO_CONFIG_3 register description.. 6.6.4 I_AUDIO_CONFIG_3 : Address : 0x5D (93) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, this register is used to config- ure the phase of the LRCK of the I2Sin. Table 18. b7 b6 b5 b4 b3 b2 b1 b0 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 Bit fields Comment CF0 Relative synchro : 0 : synchro with first data bit 1 : synchro one bit before first data bit CF1 Data reception configuration : 0 : LSB first 1 : MSB first CF2 Polarity of bit clock BCK : 0 : data provided on falling edge & stable on rising edge. 1 : data provided on rising edge & stable on falling edge CF3 Polarity of LR clock LRCK : 0 : negative 1 : positive CF4 Start value of LRCK : combined with CF3, this bit enable user to determine left/right couple according to the following table. CF[7:5] Reserved : to be set to 0. CF3 CF4 Left/Right couples 0 0 (data1/data2), (data3/data4),... 1 0 (data0/data1), (data2/data3),... 0 1 (data0/data1), (data2/data3),... 1 1 (data1/data2), (data3/data4),... b7 b6 b5 b4 b3 b2 b1 b0 LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0 b7 b6 b5 b4 b3 b2 b1 b0 000 00 0LR9 LR8 Bit fields Comment LR[4:0] Position of the data within the LRCK phase : - if CF1 = 0 (LSB), value must be set to[31 - SL[9:5] - bit position of the first bit of data within the LRCK phase]. - if CF1 = 1 (MSB), value must be set to bit position of the first bit of data within the LRCK phase. Note that range of value for this bit position is [0:31]. LR[9:5] Length-1 of the data. Max value is 31. LR[15:10] Reserved : to be set to 0 |
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