数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

STA016 数据表(PDF) 20 Page - STMicroelectronics

部件名 STA016
功能描述  MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY
PDF  43 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA016 数据表(HTML) 20 Page - STMicroelectronics

Back Button STA016 Datasheet HTML 16Page - STMicroelectronics STA016 Datasheet HTML 17Page - STMicroelectronics STA016 Datasheet HTML 18Page - STMicroelectronics STA016 Datasheet HTML 19Page - STMicroelectronics STA016 Datasheet HTML 20Page - STMicroelectronics STA016 Datasheet HTML 21Page - STMicroelectronics STA016 Datasheet HTML 22Page - STMicroelectronics STA016 Datasheet HTML 23Page - STMicroelectronics STA016 Datasheet HTML 24Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 20 / 43 page
background image
STA016A
20/43
6.6.2
I_AUDIO_CONFIG_1:
Address : 0x5B (91)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register configure the
I2Sin interface
Table 16. .
Table 17.
6.6.3
I_AUDIO_CONFIG_2 :
Address : 0x5C (92)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_3 register description..
6.6.4
I_AUDIO_CONFIG_3 :
Address : 0x5D (93)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
ure the phase of the LRCK of the I2Sin.
Table 18.
b7
b6
b5
b4
b3
b2
b1
b0
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
Bit
fields
Comment
CF0
Relative synchro :
0 : synchro with first data bit
1 : synchro one bit before first data bit
CF1
Data reception configuration :
0 : LSB first
1 : MSB first
CF2
Polarity of bit clock BCK :
0 : data provided on falling edge & stable
on rising edge.
1 : data provided on rising edge & stable
on falling edge
CF3
Polarity of LR clock LRCK :
0 : negative
1 : positive
CF4
Start value of LRCK : combined with CF3,
this bit enable user to determine left/right
couple according to the following table.
CF[7:5]
Reserved : to be set to 0.
CF3
CF4
Left/Right couples
0
0
(data1/data2), (data3/data4),...
1
0
(data0/data1), (data2/data3),...
0
1
(data0/data1), (data2/data3),...
1
1
(data1/data2), (data3/data4),...
b7
b6
b5
b4
b3
b2
b1
b0
LR7
LR6
LR5
LR4
LR3
LR2
LR1
LR0
b7
b6
b5
b4
b3
b2
b1
b0
000
00
0LR9
LR8
Bit fields
Comment
LR[4:0]
Position of the data within the LRCK
phase :
- if CF1 = 0 (LSB), value must be set to[31
- SL[9:5] - bit position of the first bit of data
within the LRCK phase].
- if CF1 = 1 (MSB), value must be set to bit
position of the first bit of data within the
LRCK phase.
Note that range of value for this bit
position is [0:31].
LR[9:5]
Length-1 of the data.
Max value is 31.
LR[15:10]
Reserved : to be set to 0



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com