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STA016 数据表(PDF) 17 Page - STMicroelectronics

部件名 STA016
功能描述  MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY
PDF  43 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA016 数据表(HTML) 17 Page - STMicroelectronics

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STA016A
Description :
This register must contain a XDIV value that enables
the system PLL to generate a frequency of 50 MHZ
for the SYSCK. See table 4.
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
6.3.5
PLL_SYSTEM_MDIV_50 :
Address : 0xEA (234)
Type : RW - DEC
Software Reset : 13
Description :
This register must contain a MDIV value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
6.3.6
PLL_SYSTEM_PEL_42_5
Address : 0xE6 (230)
Type : RW - DEC
Software Reset : 126
Description :
This register must contain a PEL value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
6.3.7
PLL_SYSTEM_PEH_42_5 :
Address : 0xE7 (231)
Type : RW - DEC
Software Reset : 223
Description :
This register must contain a PEH value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
6.3.8
6.3.9
PLL_SYSTEM_NDIV_42_5 :
Address : 0xE8 (232)
Type : RW - DEC
Software Reset : 0
Description :
This register must contain a NDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
6.3.10 PLL_SYSTEM_XDIV_42_5 :
Address : 0xE9 (233)
Type : RW - DEC
Software Reset : 1
Description :
This register must contain a XDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
6.3.11 PLL_SYSTEM_MDIV_42_5 :
Address : 0xEA (234)
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0



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