Preliminary Technical Data

AD7938/AD7939

Table 9. Analog Input Type Selection

Channel Address

MODE0 = 0, MODE1 = 0

MODE0 = 0, MODE1 = 1

MODE0 = 1, MODE1 = 0

MODE0 = 1, MODE1 = 1

Eight Single-Ended

I/P Channels

Four Fully Differential

I/P Channels

Four Pseudo-Differential I/P

Channels (Pseudo Mode 1)

Seven Pseudo-Differential I/P

Channels (Pseudo Mode 2)

ADD2

ADD1

ADD0

0

0

0

VIN0

AGND

VIN0

VIN1

VIN0

VIN1

VIN0

VIN7

0

0

1

VIN1

AGND

VIN1

VIN0

VIN1

VIN0

VIN1

VIN7

0

1

0

VIN2

AGND

VIN2

VIN3

VIN2

VIN3

VIN2

VIN7

0

1

1

VIN3

AGND

VIN3

VIN2

VIN3

VIN2

VIN3

VIN7

1

0

0

VIN4

AGND

VIN4

VIN5

VIN4

VIN5

VIN4

VIN7

1

0

1

VIN5

AGND

VIN5

VIN4

VIN5

VIN4

VIN5

VIN7

1

1

0

VIN6

AGND

VIN6

VIN7

VIN6

VIN7

VIN6

VIN7

1

1

1

VIN7

AGND

VIN7

VIN6

VIN7

VIN6

Not Allowed

SEQUENCER OPERATION

The configuration of the SEQ and SHDW bits in the control register allows the user to select a particular mode of operation of the

sequencer function. T

outlines the four modes of operation of the sequencer.

able 10

Table 10. Sequence Selection

Table 10

SEQ

SHDW

Sequence Type

0

0

This configuration is selected when the sequence function is not used. The analog input channel selected on each

individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write

operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer

function being used, where each write to the AD7938/AD7939 selects the next channel for conversion.

0

1

This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to

DB7 to the shadow register. This will program the sequence of channels to be converted continuously after each CONVST

falling edge (see the shadow register description and Table 11).

1

0

If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of the WRITE

operation. This allows other bits in the control register to be altered between conversions while in a sequence without

terminating the cycle.

1

1

This configuration is used in conjunction with the channel address bits (ADD2 to ADD0) to program continuous

conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by

the channel address bits in the control register.

SHADOW REGISTER

The shadow register on the AD7938/AD7939 is an 8-bit, write-only register. Data is loaded from DB0 to DB7 on the rising edge of WR.

The eight LSBs load into the shadow register. The information is written into the shadow register provided that the SEQ and SHDW bits

in the control register were set to 0 and 1, respectively in the previous write to the control register. Each bit represents an analog input

from Channel 0 through Channel 7. A sequence of channels may be selected through which the AD7938/AD7939 cycles with each

consecutive conversion after the write to the shadow register. To select a sequence of channels to be converted, if operating in single-

ended mode or Pseudo Mode 2, the associated channel bit in the shadow register must be set for each required analog input. When

operating in differential mode or Pseudo Mode 1, the associated pair of channels’ bits must be set for each pair of analog inputs required

in the sequence. With each consecutive CONVST pulse after the sequencer has been set up, the AD7938/AD7939 progress through the

selected channels in ascending order, beginning with the lowest channel. This continues until a write operation occurs with the SEQ and

SHDW bits configured in any way except 1, 0 (see

). When a sequence is set up in differential or Pseudo Mode 1, the ADC does

not convert on the inverse pairs (i.e., VIN1, VIN0). The bit functions of the shadow register are outlined in

. See the An

section for further information on using the sequencer.

Table 11

Table 11. Shadow Register Bit Functions

alog Input

Selection

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