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AD7939BCP 数据表(PDF) 27 Page - Analog Devices |
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AD7939BCP 数据表(HTML) 27 Page - Analog Devices |
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27 / 32 page ![]() Preliminary Technical Data AD7938/AD7939 Writing Data to the AD7938/AD7939 With W/B tied logic high, a single write operation transfers the full data-word on DB0 to DB11 to the control register on the AD7938/AD7939. The DB8/HBEN pin assumes its DB8 function. Data written to the AD7938/AD7939 should be provided on the DB0 to DB11 inputs with DB0 being the LSB of the data-word. With W/B tied logic low, the AD7938/AD7939 requires two write operations to transfer a full 12-bit word. DB8/HBEN assumes its HBEN function. Data written to the AD7938/AD7939 should be provided on the DB0 to DB7 inputs. HBEN determines whether the byte written is high byte or low byte data. The low byte of the data-word should be written first with DB0 being the LSB of the full data-word. For the high byte write, HBEN should be high and the data on the DB0 input should be data bit 8 of the 12-bit word. In both word and byte mode, a single write operation to the shadow register is always sufficient since it is only 8-bits wide. Figure 40 Figure 40. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/B = 1) shows the write cycle timing diagram of the AD7938/AD7939. When operated in word mode, the HBEN input does not exist and only the one write operation is required to write the word of data to the device. Data should be provided on DB0 to DB11. When operated in byte mode, the two write cycles shown in F are required to write the full data- word to the AD7938/AD7939. In F , the first write transfers the lower 8 bits of the data-word from DB0 to DB7, and the second write transfers the upper 4 bits of the data-word. When writing to the AD7938/AD7939, the top 4 bits in the high byte must be 0s. igure 41 igure 41 Figure 41. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/B = 0) The data is latched into the device on the rising edge of WR. The data needs to be setup a time, t7, before the WR rising edge and held for a time, t8, after the WR rising edge. The CS and WR signals are gated internally. CS and WR may be tied together as the timing specifications for t4 and t5 are 0 ns minimum (assuming CS and RD have not already been tied together). t8 t5 t7 t6 t4 DATA DB0 TO DB11 WR CS t5 t4 t7 t18 t18 t19 t19 t8 t6 t17 LOW BYTE HIGH BYTE DB0 TO DB11 HBEN/DB8 WR CS Rev. PrN | Page 27 of 32 |
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