AD7939BCP datasheet(23/32 Pages) AD

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Preliminary Technical Data

AD7938/AD7939

POWER ON

WRITE TO THE CONTROL REGISTER TO

SET UP OPERATING MODE, ANALOG INPUT

AND OUTPUT CONFIGURATION

SET SEQ = 0 SHDW = 1.

INITIATE A WRITE CYCLE.

THIS WRITE CYCLE IS TO THE SHADOW REGISTER.

SET RELEVANT BITS TO SELECT

THE CHANNELS TO BE INCLUDED IN THE SEQUENCE.

SEQ BIT = 1

SHDW BIT = 0

CONTINUOUSLY CONVERT

CONSECUTIVE

CHANNELS SELECTED

WITH EACH CONVST PULSE

BUT ALLOWS THE RANGE,

CODING, ANALOG INPUT TYPE,

ETC BITS IN THE CONTROL

WITHOUT INTERRUPTING

THE SEQUENCE.

CONTINUOUSLY CONVERT

CONSECUTIVE

CHANNELS SELECTED

IN THE SHADOW REGISTER

WITH EACH CONVST PULSE.

WR = HIGH

SEQ BIT = 0

SHDW BIT = 1

REFERENCE SECTION

The AD7938/AD7939 can operate with either the on-chip or

external reference. The internal reference is selected by setting

the REF bit in the internal control register to 1. A block diagram

of the internal reference circuitry is shown in Fi

. The

internal reference circuitry includes an on-chip 2.5 V band gap

reference and a reference buffer. When using the internal

reference, the VREFIN/VREFOUT pin should be decoupled to AGND

with a 0.47 µF capacitor. This internal reference not only

provides the reference for the analog-to-digital conversion, but

it can also be used externally in the system. It is recommended

that the reference output is buffered using an external precision

op amp before applying it anywhere in the system.

gure 36

Figure 36. Internal Reference Circuit Block Diagram

REFERENCE

AD7938/

AD7939

ADC

BUFFER

VREFIN/

VREFOUT

Figure 34. Programmable Sequence Flow Chart

Consecutive Sequence (SEQ = 1, SHDW = 1)

A sequence of consecutive channels can be converted beginning

with Channel 0 and ending with a final channel selected by

writing to the ADD2 to ADD0 bits in the control register. This

is done by setting the SEQ and SHDW bits in the control

having to write to the shadow register. Once the control register

is written to, to set this mode up, the next conversion is on

Channel 0, then Channel 1, and so on until the channel selected

by the address bits (ADD2 to ADD0) is reached. The cycle

begins again provided the WR input is tied high. If low, the SEQ

and SHDW bits must be set to 1, 0 to allow the ADC to

continue its preprogrammed sequence uninterrupted. F

shows the flow chart of the consecutive sequence mode.

Alternatively, an external reference can be applied to the

VREFIN/VREFOUT pin of the AD7938/AD7939. An external

reference input is selected by setting the REF bit in the internal

control register to 0. When using an external reference, the

VREFIN/VREFOUT pin should be decoupled to AGND with a 0.1 µF

capacitor. When operating in differential mode, the external

reference input range is 0.1 V to 3.5 V, and in all other analog

input modes, the external reference input range is 0.1 V to VDD.

In all cases, the specified reference is 2.5 V.

igure 35

Figure 35. Consecutive Sequence Mode Flow Chart

It is important to ensure that, when choosing the reference

value, the maximum analog input range (VIN MAX) is never

greater than VDD + 0.3 V to comply with the maximum ratings

of the device. In the pseudo-differential modes, the user must

ensure that VREF + VIN− ≤ VDD when using the 0 to VREF range, or

when using the 2 × VREF range that 2 × VREF + VIN− ≤ VDD.

POWER ON

WRITE TO THE CONTROL REGISTER TO

SET UP OPERATING MODE, ANALOG INPUT

AND OUTPUT CONFIGURATION SELECT

FINAL CHANNEL (ADD2 TO ADD0) IN

CONSECUTIVE SEQUENCE.

SET SEQ = 1 SHDW = 1.

CONTINUOUSLY CONVERT A CONSECUTIVE

SEQUENCE OF CHANNELS FROM CHANNEL 0

UP TO AND INCLUDING THE PREVIOUSLY

SELECTED FINAL CHANNEL ON ADD2 TO ADD0

WITH EACH CONVST PULSE.

SEQ BIT = 1

SHDW BIT = 0

CONTINUOUSLY CONVERT

CONSECUTIVE CHANNELS SELECTED

WITH EACH CONVST PULSE BUT

ALLOWS THE RANGE, CODING, ANALOG

INPUT TYPE, ETC BITS IN THE

CONTROL REGISTER TO BE CHANGED

WITHOUT INTERRUPTING

THE SEQUENCE.

The following two examples calculate the maximum VREF input

that can be used when operating the AD7938/AD7939 in

differential mode, using the 0 to VREF range with a VDD of 5 V

and 3 V, respectively.

Example 1

VIN MAX = VDD + 0.3

VIN MAX = VREF + VREF/2

If VDD = 5 V, then VIN MAX = 5.3 V.

Therefore, 3 × VREF/2 = 5.3 V.

VREF MAX = 3.5 V

Rev. PrN | Page 23 of 32

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