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AD7938/AD7939

Preliminary Technical Data

0.47

µF

+1.25V

VIN

–1.25V

+2.5V

VIN0

VIN7

VREFOUT

AD7938/

AD7939*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 24. THD vs. Analog Input Frequency for Various Source Impedances

Figure 25

Figure 25. THD vs. Analog Input Frequency for Various Supply Voltages

shows a graph of the THD versus the analog input

frequency for various supplies while sampling at 1.5 MHz with

an SCLK of 20 MHz. In this case, the source impedance is 10 Ω.

ANALOG INPUTS

The AD7938/AD7939 have software selectable analog input

configurations. The user can choose either eight single-ended

inputs, four fully differential pairs, four pseudo-differential

pairs, or seven pseudo-differential inputs. The analog input

configuration is chosen by setting the MODE0/MODE1 bits in

the internal control register (see

Table 9

Single-Ended Mode

The AD7938/AD7939 can have eight single-ended analog input

channels by setting the MODE0 and MODE1 bits in the control

impedance, it is recommended to buffer the analog input before

applying it to the ADC. The analog input range can be

programmed to be either 0 to VREF or 0 to 2 × VREF.

If the analog input signal to be sampled is bipolar, the internal

reference of the ADC can be used to externally bias up this

signal to make it of the correct format for the ADC.

Figure 26

Figure 26. Single-Ended Mode Connection Diagram

Differential Mode

The AD7938/AD7939 can have four differential analog input

pairs by setting the MODE0 and MODE1 bits in the control

Differential signals have some benefits over single-ended

signals, including noise immunity based on the device’s

common-mode rejection and improvements in distortion

performance. F

defines the fully differential analog

input of the AD7938/AD7939.

igure 27

Figure 27. Differential Input Definition

VREF

p-p

VIN+

VIN–

VREF

p-p

*ADDITIONAL PINS OMITTED FOR CLARITY

AD7938/

AD7939*

COMMON-MODE

VOLTAGE

The amplitude of the differential signal is the difference

between the signals applied to the VIN+ and VIN− pins in each

differential pair (i.e., VIN+ − VIN−). VIN+ and VIN− should be

simultaneously driven by two signals each of amplitude VREF

that are 180° out of phase (assuming the 0 to VREF range is

selected). The amplitude of the differential signal is therefore

−VREF to +VREF peak-to-peak (i.e., 2 × VREF). This is regardless of

the common mode (CM). The common mode is the average of

the two signals, i.e. (VIN+ + VIN−)/2 and is therefore the voltage

that the two inputs are centered on. This results in the span of

each input being CM ± VREF/2. This voltage has to be set up

externally and its range varies with VREF. As the value of VREF

increases, the common-mode range decreases. When driving

the inputs with an amplifier, the actual common-mode range is

determined by the amplifier’s output voltage swing.

Figure 28 and

show how the common-mode range

typically varies with VREF for a 5 V power supply using the 0 to

VREF range or 2 × VREF range, respectively. The common mode

must be in this range to guarantee the functionality of the

AD7938/AD7939.

Figure 29

shows a typical connection diagram when operating

the ADC in single-ended mode.

Rev. PrN | Page 20 of 32

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