AD7939BCP datasheet(30/32 Pages) AD

30 / 32 page

AD7938/AD7939

Preliminary Technical Data

slowed sufficiently when reading from and writing to the part to

require the insertion of one wait state. Extra wait states will be

necessary when using the TMS320C5x at their fastest clock

speeds (see the TMS320C5x User’s Guide for details).

Data is read from the ADC using the following instruction

IN D, ADC

where D is the data memory address and the ADC is the

AD7938/AD7939 address.

AD7938/

AD7939*

TMS32020/

TMS320C25/

TMS320C50*

DB11 TO DB0

DMD0 TO DMD15

A0 TO A15

READY

INTX

BUSY

CONVST

OPTIONAL

TMS320C25

ONLY

R/W

STRB

*ADDITIONAL PINS OMITTED FOR CLARITY

ADDRESS BUS

DATA BUS

ADDRESS

DECODER

MSC

Figure 47. Interfacing to the TMS32020/C25/C5x

AD7938/AD7939 to 80C186 Interface

Figure 48

Figure 48. Interfacing to the 80C186

shows the AD7938/AD7939 interfaced to the 80C186

microprocessor. The 80C186 DMA controller provides two

independent high speed DMA channels where data transfer can

occur between memory and I/O spaces. Each data transfer

consumes two bus cycles, one cycle to fetch data and the other

to store data. After the AD7938/AD7939 finish a conversion, the

BUSY line generates a DMA request to Channel 1 (DRQ1).

Because of the interrupt, the processor performs a DMA read

operation that also resets the interrupt latch. Sufficient priority

must be assigned to the DMA channel to ensure that the DMA

request is serviced before the completion of the next

conversion.

AD7938/

AD7939*

80C186*

DB0 TO DB11

AD0 TO AD15

A16 TO A19

ALE

DRQ1

BUSY

CONVST

OPTIONAL

*ADDITIONAL PINS OMITTED FOR CLARITY

ADDRESS/DATA BUS

ADDRESS BUS

DATA BUS

ADDRESS

LATCH

ADDRESS

DECODER

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