AD7939BCP datasheet(31/32 Pages) AD

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Preliminary Technical Data

AD7938/AD7939

APPLICATION HINTS

GROUNDING AND LAYOUT

The printed circuit board that houses the AD7938/AD7939

should be designed so that the analog and digital sections are

separated and confined to certain areas of the board. This

facilitates the use of ground planes that can be easily separated.

A minimum etch technique is generally best for ground planes

as it gives the best shielding. Digital and analog ground planes

should be joined in only one place, and the connection should

be a star ground point established as close to the ground pins on

the AD7938/AD7939 as possible. Avoid running digital lines

under the device as this will couple noise onto the die. The

analog ground plane should be allowed to run under the

AD7938/AD7939 to avoid noise coupling. The power supply

lines to the AD7938/AD7939 should use as large a trace as

possible to provide low impedance paths and reduce the effects

of glitches on the power supply line.

Fast switching signals, such as clocks, should be shielded with

digital ground to avoid radiating noise to other sections of the

board, and clock signals should never run near the analog

inputs. Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to each

other. This will reduce the effects of feedthrough through the

board. A microstrip technique is by far the best but is not always

possible with a double-sided board.

In this technique, the component side of the board is dedicated

to ground planes, while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should

be decoupled with 10 µF tantalum capacitors in parallel with

0.1 µF capacitors to GND. To achieve the best from these

decoupling components, they must be placed as close as

possible to the device, ideally right up against the device. The

0.1 µF capacitors should have low effective series resistance

(ESR) and effective series inductance (ESI), such as the

common ceramic types or surface-mount types, which provide

a low impedance path to ground at high frequencies to handle

transient currents due to internal logic switching.

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

The lands on the chip scale package (CP-32) are rectangular.

The printed circuit board pad for these should be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. The land should be centered on the pad.

This ensures that the solder joint size is maximized. The bottom

of the chip scale package has a thermal pad. The thermal pad on

the printed circuit board should be at least as large as this

exposed pad. On the printed circuit board, there should be a

clearance of at least 0.25 mm between the thermal pad and the

inner edges of the pad pattern. This ensures that shorting is

avoided. Thermal vias may be used on the printed circuit board

thermal pad to improve thermal performance of the package. If

vias are used, they should be incorporated in the thermal pad at

1.2 mm pitch grid. The via diameter should be between 0.3 mm

and 0.33 mm, and the via barrel should be plated with 1 oz.

copper to plug the via. The user should connect the printed

circuit board thermal pad to AGND.

EVALUATING THE AD7938/AD7939

PERFORMANCE

The recommended layout for the AD7938/AD7939 is outlined

in the evaluation board documentation. The evaluation board

package includes a fully assembled and tested evaluation board,

documentation, and software for controlling the board from the

PC via the evaluation board controller. The evaluation board

controller can be used in conjunction with the

AD7938/AD7939 evaluation board, as well as many other ADI

evaluation boards ending in the CB designator, to

demonstrate/evaluate the ac and dc performance of the

AD7938/AD7939.

The software allows the user to perform ac (fast Fourier

transform) and dc (histogram of codes) tests on the

AD7938/AD7939. The software and documentation are on the

CD that ships with the evaluation board.

Rev. PrN | Page 31 of 32

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