DP8390DV datasheet(26/56 Pages) NSC

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100 Internal Registers (Continued)

103 Register Descriptions

(Continued)

RECEIVE STATUS REGISTER (RSR)

0CH (READ)

This register records status of the received packet including information on errors and the type of address match either

physical or multicast The contents of this register are written to buffer memory by the DMA after reception of a good packet If

packets with errors are to be saved the receive status is written to memory at the head of the erroneous packet if an erroneous

packet is received If packets with errors are to be rejected the RSR will not be written to memory The contents will be cleared

when the next packet arrives CRC errors Frame Alignment errors and missed packets are counted internally by the NIC which

relinquishes the Host from reading the RSR in real time to record errors for Network Management Functions The contents of

this register are not specified until after the first reception

76543210

DFR

DIS

PHY

MPA

FAE

CRC

PRX

Bit

Symbol

Description

PRX

PACKET RECEIVED INTACT

Indicates packet received without error (Bits

CRC FAE FO and MPA are zero for the received packet)

CRC

CRC ERROR

Indicates packet received with CRC error Increments Tally

Counter (CNTR1) This bit will also be set for Frame Alignment errors

FAE

FRAME ALIGNMENT ERROR

Indicates that the incoming packet did not end

on a byte boundary and the CRC did not match at last byte boundary Increments

Tally Counter (CNTR0)

FIFO OVERRUN

This bit is set when the FIFO is not serviced causing overflow

during reception Reception of the packet will be aborted

MPA

MISSED PACKET

Set when packet intended for node cannot be accepted by

NIC because of a lack of receive buffers or if the controller is in monitor mode

and did not buffer the packet to memory Increments Tally Counter (CNTR2)

PHY

PHYSICALMULTICAST ADDRESS

Indicates whether received packet had a

physical or multicast address type

0 Physical Address Match

1 MulticastBroadcast Address Match

DIS

RECEIVER DISABLED

Set when receiver disabled by entering Monitor mode

Reset when receiver is re-enabled when exiting Monitor mode

DFR

DEFERRING

Set when CRS or COL inputs are active If the transceiver has

asserted the CD line as a result of the jabber this bit will stay set indicating the

jabber condition

Note

Following coding applies to CRC and FAE bits

FAE CRC

Type of Error

No Error (Good CRC and k6 Dribble Bits)

CRC Error

Illegal will not occur

Frame Alignment Error and CRC Error

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