DP8390DV datasheet(29/56 Pages) NSC

29 / 56 page

100 Internal Registers (Continued)

MAR0 FB7

FB6

FB5

FB4

FB3

FB2

FB1

FB0

MAR1 FB15 FB14 FB13 FB12 FB11 FB10 FB9

FB8

MAR2 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16

MAR3 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24

MAR4 FB39 FB38 FB37 FB36 FB35 FB34 FB33 FB32

MAR5 FB47 FB46 FB45 FB44 FB43 FB42 FB41 FB40

MAR6 FB55 FB54 FB53 FB52 FB51 FB50 FB49 FB48

MAR7 FB63 FB62 FB61 FB60 FB59 FB58 FB57 FB56

If address Y is found to hash to the value 32 (20H) then

FB32 in MAR4 should be initialized to ‘‘1’’ This will cause

the NIC to accept any multicast packet with the address Y

NETWORK TALLY COUNTERS

Three 8-bit counters are provided for monitoring the number

of CRC errors Frame Alignment Errors and Missed Pack-

ets The maximum count reached by any counter is 192

(C0H) These registers will be cleared when read by the

CPU The count is recorded in binary in CT0 – CT7 of each

Tally Register

Frame Alignment Error Tally (CNTR0)

This counter is incremented every time a packet is received

with a Frame Alignment Error The packet must have been

recognized by the address recognition logic The counter is

cleared after it is read by the processor

76543210

CNTR0 CT7

CT6

CT5

CT4

CT3

CT2

CT1

CT0

CRC Error Tally (CNTR1)

This counter is incremented every time a packet is received

with a CRC error The packet must first be recognized by

the address recognition logic The counter is cleared after it

is read by the processor

76543210

CNTR1 CT7

CT6

CT5

CT4

CT3

CT2

CT1

CT0

Frames Lost Tally Register (CNTR2)

This counter is incremented if a packet cannot be received

due to lack of buffer resources In monitor mode this coun-

ter will count the number of packets that pass the address

recognition logic

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CNTR2 CT7

CT6

CT5

CT4

CT3

CT2

CT1

CT0

FIFO

This is an eight bit register that allows the CPU to examine

the contents of the FIFO after loopback The FIFO will con-

tain the last 8 data bytes transmitted in the loopback packet

Sequential reads from the FIFO will advance a pointer in the

FIFO and allow reading of all 8 bytes

76543210

FIFO DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Note

The FIFO should only be read when the NIC has been programmed in

loopback mode

NUMBER OF COLLISIONS (NCR)

This register contains the number of collisions a node expe-

riences when attempting to transmit a packet If no colli-

sions are experienced during a transmission attempt the

COL bit of the TSR will not be set and the contents of NCR

will be zero If there are excessive collisions the ABT bit in

the TSR will be set and the contents of NCR will be zero

The NCR is cleared after the TXP bit in the CR is set

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NCR

NC3

NC2

NC1

NC0

110 Initialization Procedures

The NIC must be initialized prior to transmission or recep-

tion of packets from the network Power on reset is applied

to the NIC’s reset pin This clearssets the following bits

Reset Bits

Set Bits

Command Register (CR)

TXP STA

RD2 STP

Interrupt Status (ISR)

RST

Interrupt Mask (IMR)

All Bits

Data Control (DCR)

LAS

Transmit Config (TCR)

LB1 LB0

The NIC remains in its reset state until a Start Command is

issued This guarantees that no packets are transmitted or

received and that the NIC remains a bus slave until all ap-

propriate internal registers have been programmed After

initialization the STP bit of the command register is reset

and packets may be received and transmitted

Initialization Sequence

The following initialization procedure is mandatory

1) Program Command Register for Page 0 (Command

2) Initialize Data Configuration Register (DCR)

3) Clear Remote Byte Count Registers (RBCR0 RBCR1)

4) Initialize Receive Configuration Register (RCR)

5) Place the NIC in LOOPBACK mode 1 or 2 (Transmit

Configuration Register e 02H or 04H)

6) Initialize

Receive

Buffer

Ring

Boundary

Pointer

(BNDRY)

Page Start (PSTART)

and Page Stop

(PSTOP)

7) Clear Interrupt Status Register (ISR) by writing 0FFh to

8) Initialize Interrupt Mask Register (IMR)

9) Program Command Register for page 1 (Command

i)Initialize Physical Address Registers (PAR0-PAR5)

ii)Initialize Multicast Address Registers (MAR0-MAR7)

iii)Initialize CURRent pointer

10) Put NIC in START mode (Command Register e 22H)

The local receive DMA is still not active since the NIC is

in LOOPBACK

11) Initialize the Transmit Configuration for the intended val-

ue The NIC is now ready for transmission and recep-

tion

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