DP8390DV datasheet(31/56 Pages) NSC

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120 Loopback Diagnostics (Continued)

Alignment of the Received Packet in the FIFO

Reception of the packet in the FIFO begins at location zero

after the FIFO pointer reaches the last location in the FIFO

the pointer wraps to the top of the FIFO overwriting the

previously received data This process continues until the

last byte is received The NIC then appends the received

byte count in the next two locations of the FIFO The con-

tents of the Upper Byte Count are also copied to the next

FIFO location The number of bytes used in the loopback

packet determines the alignment of the packet in the FIFO

The alignment for a 64-byte packet is shown below

FIFO

LOCATION

CONTENTS

LOWER BYTE COUNT

First Byte Read

UPPER BYTE COUNT

x Second Byte Read

UPPER BYTE COUNT

LAST BYTE

CRC1

CRC2

CRC3

CRC4

Last Byte Read

For the following alignment in the FIFO the packet length

should be (N c 8) a 5 Bytes Note that if the CRC bit in the

TCR is set CRC will not be appended by the transmitter If

the CRC is appended by the transmitter the last four bytes

bytes N-3 to N correspond to the CRC

FIFO

LOCATION

CONTENTS

BYTE N-4

First Byte Read

BYTE N-3 (CRC1)

Second Byte Read

BYTE N-2 (CRC2)

BYTE N-1 (CRC3)

BYTE N (CRC4)

LOWER BYTE COUNT

UPPER BYTE COUNT

Last Byte Read

UPPER BYTE COUNT

LOOPBACK TESTS

Loopback capabilities are provided to allow certain tests to

be performed to validate operation of the DP8390D NIC pri-

or to transmitting and receiving packets on a live network

Typically these tests may be performed during power up of

a node The diagnostic provides support to verify the follow-

ing

1) Verify integrity of data path Received data is checked

against transmitted data

2) Verify CRC logic’s capability to generate good CRC on

transmit verify CRC on receive (good or bad CRC)

3) Verify that the Address Recognition Logic can

a) Recognize address match packets

b) Reject packets that fail to match an address

LOOPBACK OPERATION IN THE NIC

Loopback is a modified form of transmission using only half

of the FIFO This places certain restrictions on the use of

loopback testing When loopback mode is selected in the

TCR the FIFO is split A packet should be assembled in

memory with programming of TPSR and TBCR0TBCR1

registers When the transmit command is issued the follow-

ing operations occur

Transmitter Actions

1) Data is transferred from memory by the DMA until the

FIFO is filled For each transfer TBCR0 and TBCR1 are

decremented (Subsequent burst transfers are initiated

when the number of bytes in the FIFO drops below the

programmed threshold)

2) The NIC generates 56 bits of preamble followed by an

8-bit synch pattern

3) Data transferred from FIFO to serializer

4) If CRCe1 in TCR no CRC calculated by NIC the last

byte transmitted is the last byte from the FIFO (Allows

software CRC to be appended) If CRCe0 NIC calcu-

lates and appends four bytes of CRC

5) At end of Transmission PTX bit set in ISR

Receiver Actions

1) Wait for synch all preamble stripped

2) Store packet in FIFO increment receive byte count for

each incoming byte

3) If CRCe0 in TCR receiver checks incoming packet for

CRC errors If CRCe1 in TCR receiver does not check

CRC errors CRC error bit always set in RSR (for address

matching packets)

4) At end of receive receive byte count written into FIFO

receive status register is updated The PRX bit is typically

set in the RSR even if the address does not match If

CRC errors are forced the packet must match the ad-

dress filters in order for the CRC error bit in the RS to be

set

EXAMPLES

The following examples show what results can be expected

from a properly operating NIC during loopback The restric-

tions and results of each type of loopback are listed for

reference The loopback tests are divided into two sets of

tests One to verify the data path CRC generation and byte

count through all three paths The second set of tests uses

internal loopback to verify the receiver’s CRC checking and

address recognition For all of the tests the DCR was pro-

grammed to 40h

PATH

TCR

RCR

TSR

RSR

ISR

NIC Internal

53(1)

02(2)

02(3)

Note 1

Since carrier sense and collision detect inputs are blocked during

internal loopback carrier and CD heartbeat are not seen and the CRS and

CDH bits are set

Note 2

CRC errors are always indicated by receiver if CRC is appended by

the transmitter

Note 3

Only the PTX bit in the ISR is set the PRX bit is only set if status is

written to memory In loopback this action does not occur and the PRX bit

remains 0 for all loopback modes

Note 4

All values are hex

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