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DP8390DV 数据表(PDF) 42 Page - National Semiconductor (TI) |
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DP8390DV 数据表(HTML) 42 Page - National Semiconductor (TI) |
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42 / 56 page ![]() 150 Switching Characteristics (Continued) Register Write (Non Latched ADS0 e 1) TLF8582 – 79 Symbol Parameter Min Max Units rsws Register Select to Write Setup 15 ns (Note 1) rswh Register Select Hold from Write 0 ns rwds Register Write Data Setup 20 ns rwdh Register Write Data Hold 21 ns wackl Write Low to ACK Low n bcyc a 30 ns (Note 2) wackh Write High to ACK High 30 ns ww Write Width from ACK 50 ns Note 1 Assumes ADS0 is high when RA0–3 changing Note 2 ACK is not generated until CS and SWR are low and the NIC has synchronized to the register access In Dual Bus systems additional cycles will be used for a local DMA or remote DMA to complete 42 |
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