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TMS320DM640 数据表(PDF) 70 Page - Texas Instruments |
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TMS320DM640 数据表(HTML) 70 Page - Texas Instruments |
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70 / 171 page ![]() Device Configurations 70 June 2003 − Revised August 2004 SPRS222C 31 24 Reserved R-0 23 16 Reserved R-0 15 8 Reserved R-0 76 54 3 21 0 Reserved Reserved VP1EN† VP0EN I2C0EN MCBSP1EN MCBSP0EN MCASP0EN R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 Legend: R = Read only; R/W = Read/Write; -n = value after reset † The DM640 device does not support the VP1 peripheral; therefore, this bit is Reserved. Figure 2−1. Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 − 0x01B3F003] Table 2−3. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions BIT NAME DESCRIPTION 31:6 Reserved Reserved. Read-only, writes have no effect. 5 VP1EN VP1 Enable bit [DM641 only]. Determines whether the VP1 peripheral is enabled or disabled. 0 = VP1 is disabled, and the module is powered down (default). (This feature allows power savings by disabling the peripheral when not in use.) 1 = VP1 is enabled. The DM640 device does not support the VP1 peripheral; therefore, this bit is Reserved. 4 VP0EN VP0 Enable bit. Determines whether the VP0 peripheral is enabled or disabled. 0 = VP0 is disabled, and the module is powered down (default). (This feature allows power savings by disabling the peripheral when not in use.) 1 = VP0 is enabled. 3 I2C0EN Inter-integrated circuit 0 (I2C0) enable bit. Selects whether I2C0 peripheral is enabled or disabled (default). 0 = I2C0 is disabled, and the module is powered down (default). 1 = I2C0 is enabled. 2 MCBSP1EN Video Port 1 (VP1) lower data pins vs. McBSP1 enable bit. Selects whether VP1 peripheral lower-data pins or the McBSP1 peripheral is enabled. 0 = VP1 lower-data pins are enabled and function (if VP1EN=1), McBSP1 is disabled; the remaining VP1 upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit settings. 1 = McBSP1 is enabled, VP1 lower-data pin functions are disabled (default). For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and the signal pins controlled/selected, see Figure 2−2. |
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