TMS320DM640 datasheet(71/171 Pages) TI

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Device Configurations

June 2003 − Revised August 2004

SPRS222C

Table 2−3. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions (Continued)

DESCRIPTION

NAME

BIT

MCBSP0EN

Video Port 0 (VP0) lower data pins vs. McBSP0 enable bit.

Selects whether VP0 peripheral lower-data pins or the McBSP1 peripheral is enabled.

= VP0 lower-data pins are enabled and function (if VP0EN=1), McBSP0 is disabled; the

remaining VP0 upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit

settings.

= McBSP0 is enabled, VP0 lower-data pin functions are disabled (default).

For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and

the signal pins controlled/selected, see Figure 2−2.

MCASP0EN

McASP0 select bit.

Selects whether the McASP0 peripheral or the VP0 and VP1 upper-data pins are enabled.

= Reserved [default].

= McASP0 is enabled.

For proper DM641/DM640 device operation, the pin must be set to a “1”.

VP0 Data (8 pins)

VP0 (Channel A)

McBSP0

McBSP0EN [PERCFG.1]

VP1 Data (8 pins)

VP1 (Channel A) [DM641 Only]

McBSP1

McBSP1EN [PERCFG.2]

VP0D[6:0] Muxed†

VP0D[7] Standalone

VP1D[6:0] Muxed‡

VP1D[7] Standalone

† Consists of: VP0D[6]/CLKR0, VP0D[5]/FSR0, VP0D[4]/DR0, VP0D[3]/CLKS0, VP0D[2]/DX0, VP0D[1]/FSX0, VP0D[0]/CLKX0.

‡ Consists of: VP1D[6]/CLKR1, VP1D[5]/FSR1, VP1D[4]/DR1, VP1D[3]/CLKS1, VP1D[2]/DX1, VP1D[1]/FSX1, VP1D[0]/CLKX1.

Figure 2−2. VP1, VP0, McBSP1, and McBSP0 Pin Muxing

TMS320DM640 数据表(PDF) 71 Page - Texas Instruments

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