TMS320DM640 datasheet(16/171 Pages) TI

16 / 171 page

Description

June 2003 − Revised August 2004

SPRS222C

1.2

Description

The TMS320C64x

 DSPs (including the TMS320DM641 and TMS320DM640 devices) are the

highest-performance fixed-point DSP generation in the TMS320C6000

 DSP platform. The TMS320DM641

(DM641) and TMS320DM640 (DM640) devices are based on the second-generation high-performance,

advanced VelociTI

 very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas

Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x

 is a

code-compatible member of the C6000

 DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641

device offers cost-effective solutions to high-performance DSP programming challenges.

With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the DM640

device offers cost-effective solutions to high-performance DSP programming challenges.

The DM641/DM640 DSP possesses the operational flexibility of high-speed controllers and the numerical

capability of array processors. The C64x

 DSP core processor has 64 general-purpose registers of 32-bit

word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic

logic units (ALUs)— with VelociTI.2

 extensions. The VelociTI.2 extensions in the eight functional units

include new instructions to accelerate the performance in video and imaging applications and extend the

parallelism of the VelociTI

 architecture. The DM641 can produce four 16-bit multiply-accumulates (MACs)

per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of

4800 MMACS. The DM640 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of

1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The

DM641/DM640 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip

peripherals similar to the other C6000

 DSP platform devices.

The DM641/DM640 uses a two-level cache-based architecture and has a powerful and diverse set of

peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache

(L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1-Mbit memory

space that is shared between program and data space. L2 memory can be configured as mapped memory,

cache, or combinations of the two. The peripheral set includes: two configurable video ports (DM641); one

configurable video port (DM640); a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output

(MDIO) module; a VCXO interpolated control port (VIC); one 4-bit multichannel buffered audio serial port

(McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs);

three 32-bit general-purpose timers; a 16-bit host-port interface (HPI16) [DM641]; an 8-pin general-purpose

input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external

memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and

peripherals.

The DM641 device has two single-channel 8-bit configurable video port peripherals (VP0 and VP1). The

DM640 device has one single-channel 8-bit configurable video port peripheral (VP0). These video port

peripherals provide a glueless interface to common video decoder and encoder devices. The DM641/DM640

video port peripherals support multiple resolutions and video standards (e. g., CCIR601 and ITU−BT.656).

These video port peripherals are configurable and can support either video capture and/or video display

modes.

For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated

Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with four serial data pins which can be

individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin

from 2 to 32 time slots. The DM641/DM640 has sufficient bandwidth to support all 4 serial data pins

transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple

serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S)

format.

TMS320C6000, and C6000 are trademarks of Texas Instruments.

TMS320DM640 数据表(PDF) 16 Page - Texas Instruments

TMS320DM640 数据表(HTML) 16 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载