PCF88331 datasheet(70/112 Pages) PHILIPS

70 / 112 page

2003 Feb 14

Philips Semiconductors

Objective speciﬁcation

STN RGB - 132

× 132 × 3 driver

PCF8833

SERIAL INTERFACE

Communication with the microcontroller can also occur via

a clock-synchronized serial peripheral interface. The

selection of this interface is achieved with pin PS0; see

Section 7.1.1.

The serial interface is a 3-line bidirectional interface for

communication between the microcontroller and the LCD

driver chip. The 3 lines are chip enable (SCE), Serial

Clock (SCLK) and Serial Data (SD). The PCF8833 is

connected to the SD pin of the microcontroller by two pins

SDIN (data input) and SDOUT (data output) which are

connected together.

9.1

Write mode

The Write mode of the interface means that the

microcontroller writes commands and data to the

PCF8833. Each data packet contains a control bit D/C and

a transmission byte. If bit D/C is logic 0, the following byte

is interpreted as a command byte. The command set is

given in Table 1. If bit D/C is logic 1, the following bytes are

stored in the display data RAM or registers. After every

RAM data byte the address counter increments

automatically. Figure 42 shows the general format of the

Write mode and the definition of the transmission byte.

Any instruction can be sent in any order to the PCF8833;

the MSB is transmitted first. The serial interface is

initialized when SCE is HIGH. In this state, SCLK pulses

have no effect and no power is consumed by the serial

interface. A falling edge on pin SCE enables the serial

interface and indicates the start of data transmission.

Figure 42 shows the protocol of the Write mode:

• When SCE is HIGH, SCLKs are ignored. The serial

interface is initialized during the HIGH time of SCE.

• At the falling edge of SCE SCLK must be LOW (see

Fig.51)

• SDIN is sampled at the rising edge of SCLK

• D/C indicates, whether the byte is a command (D/C=0)

or data (D/C = 1). It is sampled with the first rising SCLK

edge.

• If SCE stays LOW after the last bit of a data/command

byte, the serial interface will receive the D/C bit of the

next byte at the next rising edge of SCLK (see Fig.43).

• A reset pulse at pin RES interrupts the transmission.

The data being written into the RAM may be corrupted.

The registers are cleared. If SCE is LOW after the rising

edge of RES, the serial interface is ready to receive the

D/C bit of a data/command byte; see Figs 44 and 50.

handbook, full pagewidth

MGU958

MSB

LSB

transmission byte (TB)

may be a command OR a data byte

D/C

Fig.42 Serial data stream, Write mode.

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