PCF88331 datasheet(87/112 Pages) PHILIPS

87 / 112 page

2003 Feb 14

Philips Semiconductors

Objective speciﬁcation

STN RGB - 132

× 132 × 3 driver

PCF8833

15.5

Interface commands

Table 94 contains a list of all OTP related commands.

Table 94 OTP related commands

Note

1. X = don’t care. For hexadecimal representation, don’t care bits are assumed to be 0.

NAME

D/C

COMMAND BYTE(1)

HEX

DESCRIPTION

CALMM

CALMM command

ORA2 ORA1 ORA0

OPE

CALMM

entry CALMM mode

(CALMM) enable

programming (OPE) set

address (ORA)

Sleep_OUT

generate a refresh of the

OTP if CALMM = 0

OTPSHTIN

start shifting data in the shift

executed as long as D/C=1

SFD

EE/EF set factory default (see

Sections 6.2.47 and 15.2)

15.5.1

CALIBRATION MODULE MAKER MODE

When CALMM = 1 the device enters the calibration

module maker mode. This mode enables the filling of the

OTP matrix and allows programming of the non-volatile

OTP cells to take place.

The VOTP(drain) pad is not connected directly to the OTP

cells, but through a switch that must be closed for

programming by setting OPE to logic 1.

The OTP row to be programmed may be chosen by setting

the OTP row address ORA[2:0].

15.5.2

REFRESH

The action of the refresh instruction is to force the registers

of the OTP matrix to load the value from the non-volatile

part of the OTP cell. This instruction takes up to 1 ms to

complete. During this time all other instructions may be

sent.

In the PCF8833 the refresh instruction is associated with

the Sleep_OUT instruction such that the shift register is

automatically refreshed every time the Sleep_OUT

instruction is sent.

No refresh may be started when in CALMM mode, i.e.

whenever CALMM = 1.

15.5.3

SHIFT IN

The OTP matrix (see Table 90) is filled using the

OTPSHTIN command, which is similar to the RAM write

command. First the appropriate command is sent, then the

following data bytes are shifted bytewise into the OTP

matrix from left to right, i.e. the new byte is loaded into

byte 0, whereas the data of byte 0 is shifted into byte 1 and

so on. Bit 7 of the data is not used. The shifting is enabled

as long as D/C remains at logic 1.

15.6

Suggestion on how to calibrate VLCD2 using

MMVOP

In order to calibrate the programming of VLCD2, the

sequence in Table 95 is suggested to determine what

MMVOP value has to be programmed.

It is assumed that the relevant parameters, the VLCD2

programming, VPR and the number of stages S, are set via

the interface. This implies that SFD is set to logic 0 and

that all OTP settings except MMVOP are ignored.

PCF88331 数据表(PDF) 87 Page - NXP Semiconductors

PCF88331 数据表(HTML) 87 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载