PCF88331 datasheet(13/112 Pages) PHILIPS

13 / 112 page

2003 Feb 14

Philips Semiconductors

Objective speciﬁcation

STN RGB - 132

× 132 × 3 driver

PCF8833

6.2

Function set

6.2.1

NO OPERATION

No operation (NOP) has no effect on internal data or settings. However, it can be used to terminate data transfer (read

and write).

Table 3

No operation command bits

D/C

76543210

DEFAULT

000000000

00H

6.2.2

RESET

The PCF8833 has a hardware and a software reset. After

power-up a hardware reset (pin RES) must be applied; see

Fig.50. The hardware and software resets give the same

results. After a reset, the chip has the following state:

• All LCD outputs are set to VSS (display off)

• RAM data unchanged

• Power-down mode (Sleep_IN)

• Command register set to default states; see Table 4

• Interface pins are set to inputs.

After a reset, care must be taken with respect to the reset

timing constraints (see Fig.50) when the PCF8833 is

powered-up. The power-up must be done by sending the

Sleep_OUT command.

After a power-up the display RAM content is undefined.

Neither a hardware reset nor a software reset changes the

data that is stored in the display RAM. Sending display

data must stop 160 ns before issuing a hardware reset,

otherwise the last word written to the display RAM may be

corrupted. The row and column outputs are tied to VSS1

with a reset because power-down (Sleep_IN) is in the

reset state.

Table 4

Reset state after hardware and software reset

COMMAND

DESCRIPTION

RESET STATE

Sleep_IN

PCF8833 is in Sleep_IN mode (booster and display are switched off)

−

INVOFF

display inversion is off

−

BSTRON

when Sleep_OUT is active; booster is switched on

−

DISPON

when Sleep_OUT is active; display is turned on

−

TEOFF

tearing effect line pulse is turned off

−

IDMOFF

Idle mode is turned off (4 kbyte colour mode, not 8-colour mode)

−

NORON

Normal mode is active, not Scroll or Partial mode

−

RAM write in X direction

no mirror Y

RGB

colour order is RGB

no mirror X

LAO

line address order (top to bottom)

BRS

bottom rows are not mirrored; note 1

TRS

top rows are not mirrored; note 1

FINV

super frame inversion is on

DOR

normal data order

TCDFE

DF temperature compensation switched on

TCVOPE

VOP temperature compensation switched on

internal oscillator

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