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TPS51116MPWPREP 数据表(PDF) 1 Page - Texas Instruments |
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TPS51116MPWPREP 数据表(HTML) 1 Page - Texas Instruments |
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1 / 38 page ![]() TPS51116-EP www.ti.com SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012 COMPLETE DDR, DDR2, DDR3, AND LPDDR3 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 1-A LDO, BUFFERED REFERENCE Check for Samples: TPS51116-EP 1 FEATURES 2 • Synchronous Buck Controller (VDDQ) APPLICATIONS – Wide-Input Voltage Range: 3.0-V to 28-V • DDR/DDR2/DDR3/LPDDR3 Memory Power Supplies – D −CAP™ Mode with 100-ns Load Step Response • SSTL-2, SSTL-18, SSTL-15 and HSTL Termination – Current Mode Option Supports Ceramic Output Capacitors SUPPORTS DEFENSE, AEROSPACE, – Supports Soft-Off in S4/S5 States AND MEDICAL APPLICATIONS – Current Sensing from RDS(on) or Resistor • Controlled Baseline – 2.5-V (DDR), 1.8-V (DDR2), Adjustable to • One Assembly and Test Site 1.5-V (DDR3) or 1.2-V (LPDDR3) or Output Range 0.75-V to 3.0-V • One Fabrication Site – Equipped with Powergood, Overvoltage • Available in Military (–55°C to 125°C) Protection and Undervoltage Protection Temperature Range • 1-A LDO (VTT), Buffered Reference (VREF) • Extended Product Life Cycle – Capable to Sink and Source 1 A • Extended Product-Change Notification – LDO Input Available to Optimize Power • Product Traceability Losses – Requires only 20- μF Ceramic Output Capacitor – Buffered Low Noise 10-mA VREF Output – Accuracy ±20 mV for both VREF and VTT – Supports High-Z in S3 and Soft-Off in S4/S5 – Thermal Shutdown DESCRIPTION The TPS51116 provides a complete power supply for DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, and LPDDR3 memory systems. It integrates a synchronous buck controller with a 1-A sink/source tracking linear regulator and buffered low noise reference. The TPS51116 offers the lowest total solution cost in systems where space is at a premium. The TPS51116 synchronous controller runs fixed 400-kHz, pseudo-constant frequency PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest transient response or in current mode to support ceramic output capacitors. The 1-A sink/source LDO maintains fast transient response only requiring 20- μF (2 × 10 μF) of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The TPS51116 supports all of the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 (suspend to disk). TPS51116 has all of the protection features including thermal shutdown and is offered in a 20-pin HTSSOP PowerPAD™ package. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 D-CAP, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2012, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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