TPS51116-EP

SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012

www.ti.com

PWM Frequency and Adaptive On-Time Control

TPS51116 includes an adaptive on-time control scheme and does not have a dedicated oscillator on board.

However, the device runs with fixed 400-kHz pseudo-constant frequency by feed-forwarding the input and output

voltage into the on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and

Although the TPS51116 does not have a pin connected to VIN, the input voltage is monitored at LL pin during

the ON state. This helps pin count reduction to make the part compact without sacrificing its performance. In

order to secure minimum ON-time during startup, feed-forward from the output voltage is enabled after the output

becomes 750 mV or larger.

VDDQ Output Voltage Selection

Table 1. VDDQSET and Output Voltages

VDDQSET

VDDQ (V)

VTTREF and VTT

NOTE

GND

2.5

DDR

V5IN

1.8

DDR2

FB Resistors

Adjustable

(1) (2)

VTT Linear Regulator and VTTREF

TPS51116 integrates high performance low-dropout linear regulator that is capable of sourcing and sinking

current up to 1 A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramic

capacitors are enough to keep tracking the VTTREF within ±40 mV at all conditions including fast load transient.

To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should

be connected to the positive node of VTT output capacitor(s) as a separate trace from VTT pin. For stable

operation, total capacitance of the VTT output terminal can be equal to or greater than 20

μF. It is recommended

to attach two 10-

μF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If ESR of the output

capacitor is greater than 2 m

Ω, insert an RC filter between the output and the VTTSNS input to achieve loop

stability. The RC filter time constant should be almost the same or slightly lower than the time constant made by

the output capacitor and its ESR. VTTREF block consists of on-chip 1/2 divider, LPF and buffer. This regulator

also has sink and source capability up to 10 mA. Bypass VTTREF to GND by a 0.033-

μF ceramic capacitor for

stable operation.

When VTT is not required in the design, following treatment is strongly recommended.

•

Connect VLDOIN to VDDQSNS.

•

Tie VTTSNS to VTT, and remove capacitors from VTT to float.

•

Connect VTTGND and MODE to GND (Non-tracking discharge mode as shown in Table 3)

•

Maintain a 0.033-µF capacitor connected at VTTREF.

•

Pull down S3 to GND with 1 k

Ω of resistance.

A typical circuit for this application is shown in Figure 2

(1)

(2)

Including DDR3 and LPDDR3

12

Submit Documentation Feedback

Copyright © 2012, Texas Instruments Incorporated

Product Folder Links: TPS51116-EP